wrap_pll_config.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Marek Vasut <marex@denx.de>
  4. */
  5. #include <common.h>
  6. #include <asm/arch/clock_manager.h>
  7. #include <qts/pll_config.h>
  8. #define MAIN_VCO_BASE ( \
  9. (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
  10. CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
  11. (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
  12. CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
  13. )
  14. #define PERI_VCO_BASE ( \
  15. (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
  16. CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
  17. (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
  18. CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
  19. (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
  20. CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
  21. )
  22. #define SDR_VCO_BASE ( \
  23. (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
  24. CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
  25. (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
  26. CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
  27. (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
  28. CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
  29. )
  30. static const struct cm_config cm_default_cfg = {
  31. /* main group */
  32. MAIN_VCO_BASE,
  33. (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
  34. CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
  35. (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
  36. CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
  37. (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
  38. CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
  39. (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
  40. CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
  41. (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
  42. CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  43. (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
  44. CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
  45. (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
  46. CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
  47. (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
  48. CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
  49. (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
  50. CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
  51. (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
  52. CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
  53. (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
  54. CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
  55. (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
  56. CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
  57. (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
  58. CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
  59. (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
  60. CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
  61. (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
  62. CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
  63. /* peripheral group */
  64. PERI_VCO_BASE,
  65. (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
  66. CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
  67. (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
  68. CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
  69. (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
  70. CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
  71. (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
  72. CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  73. (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
  74. CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
  75. (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
  76. CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
  77. (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
  78. CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
  79. (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
  80. CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
  81. (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
  82. CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
  83. (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
  84. CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
  85. (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
  86. CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
  87. (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
  88. CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
  89. (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
  90. CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
  91. (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
  92. CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
  93. /* sdram pll group */
  94. SDR_VCO_BASE,
  95. (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
  96. CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
  97. (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
  98. CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
  99. (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
  100. CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
  101. (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
  102. CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
  103. (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
  104. CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
  105. (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
  106. CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
  107. (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
  108. CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
  109. (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
  110. CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
  111. /* altera group */
  112. CONFIG_HPS_ALTERAGRP_MPUCLK,
  113. };
  114. const struct cm_config * const cm_get_default_config(void)
  115. {
  116. return &cm_default_cfg;
  117. }
  118. const unsigned int cm_get_osc_clk_hz(const int osc)
  119. {
  120. if (osc == 1)
  121. return CONFIG_HPS_CLK_OSC1_HZ;
  122. else if (osc == 2)
  123. return CONFIG_HPS_CLK_OSC2_HZ;
  124. else
  125. return 0;
  126. }
  127. const unsigned int cm_get_f2s_per_ref_clk_hz(void)
  128. {
  129. return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
  130. }
  131. const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
  132. {
  133. return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
  134. }