cpu.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * (C) Copyright 2009
  7. * Marvell Semiconductor <www.marvell.com>
  8. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <asm/cache.h>
  16. #include <asm/io.h>
  17. #include <u-boot/md5.h>
  18. #include <asm/arch/cpu.h>
  19. #define BUFLEN 16
  20. void reset_cpu(unsigned long ignored)
  21. {
  22. struct orion5x_cpu_registers *cpureg =
  23. (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
  24. writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  25. &cpureg->rstoutn_mask);
  26. writel(readl(&cpureg->sys_soft_rst) | 1,
  27. &cpureg->sys_soft_rst);
  28. while (1)
  29. ;
  30. }
  31. /*
  32. * Compute Window Size field value from size expressed in bytes
  33. * Used with the Base register to set the address window size and location.
  34. * Must be programmed from LSB to MSB as sequence of ones followed by
  35. * sequence of zeros. The number of ones specifies the size of the window in
  36. * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
  37. * NOTES:
  38. * 1) A sizeval equal to 0x0 specifies 4 GiB.
  39. * 2) A return value of 0x0 specifies 64 KiB.
  40. */
  41. unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
  42. {
  43. /*
  44. * Calculate the number of 64 KiB blocks needed minus one (rounding up).
  45. * For sizeval > 0 this is equivalent to:
  46. * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
  47. */
  48. sizeval = (sizeval - 1) >> 16;
  49. /*
  50. * Propagate 'one' bits to the right by 'oring' them.
  51. * We need only treat bits 15-0.
  52. */
  53. sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
  54. sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
  55. sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
  56. sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
  57. return sizeval;
  58. }
  59. /*
  60. * orion5x_config_adr_windows - Configure address Windows
  61. *
  62. * There are 8 address windows supported by Orion5x Soc to addess different
  63. * devices. Each window can be configured for size, BAR and remap addr
  64. * Below configuration is standard for most of the cases
  65. *
  66. * If remap function not used, remap_lo must be set as base
  67. *
  68. * NOTES:
  69. *
  70. * 1) in order to avoid windows with inconsistent control and base values
  71. * (which could prevent access to BOOTCS and hence execution from FLASH)
  72. * always disable window before writing the base value then reenable it
  73. * by writing the control value.
  74. *
  75. * 2) in order to avoid losing access to BOOTCS when disabling window 7,
  76. * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
  77. * then configure windows 6 for its own target.
  78. *
  79. * Reference Documentation:
  80. * Mbus-L to Mbus Bridge Registers Configuration.
  81. * (Sec 25.1 and 25.3 of Datasheet)
  82. */
  83. int orion5x_config_adr_windows(void)
  84. {
  85. struct orion5x_win_registers *winregs =
  86. (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
  87. /* Disable window 0, configure it for its intended target, enable it. */
  88. writel(0, &winregs[0].ctrl);
  89. writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
  90. writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
  91. writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
  92. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
  93. ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
  94. ORION5X_WIN_ENABLE), &winregs[0].ctrl);
  95. /* Disable window 1, configure it for its intended target, enable it. */
  96. writel(0, &winregs[1].ctrl);
  97. writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
  98. writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
  99. writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
  100. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
  101. ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
  102. ORION5X_WIN_ENABLE), &winregs[1].ctrl);
  103. /* Disable window 2, configure it for its intended target, enable it. */
  104. writel(0, &winregs[2].ctrl);
  105. writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
  106. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
  107. ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
  108. ORION5X_WIN_ENABLE), &winregs[2].ctrl);
  109. /* Disable window 3, configure it for its intended target, enable it. */
  110. writel(0, &winregs[3].ctrl);
  111. writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
  112. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
  113. ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
  114. ORION5X_WIN_ENABLE), &winregs[3].ctrl);
  115. /* Disable window 4, configure it for its intended target, enable it. */
  116. writel(0, &winregs[4].ctrl);
  117. writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
  118. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
  119. ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
  120. ORION5X_WIN_ENABLE), &winregs[4].ctrl);
  121. /* Disable window 5, configure it for its intended target, enable it. */
  122. writel(0, &winregs[5].ctrl);
  123. writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
  124. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
  125. ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
  126. ORION5X_WIN_ENABLE), &winregs[5].ctrl);
  127. /* Disable window 6, configure it for FLASH, enable it. */
  128. writel(0, &winregs[6].ctrl);
  129. writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
  130. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
  131. ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
  132. ORION5X_WIN_ENABLE), &winregs[6].ctrl);
  133. /* Disable window 7, configure it for FLASH, enable it. */
  134. writel(0, &winregs[7].ctrl);
  135. writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
  136. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
  137. ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
  138. ORION5X_WIN_ENABLE), &winregs[7].ctrl);
  139. /* Disable window 6, configure it for its intended target, enable it. */
  140. writel(0, &winregs[6].ctrl);
  141. writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
  142. writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
  143. ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
  144. ORION5X_WIN_ENABLE), &winregs[6].ctrl);
  145. return 0;
  146. }
  147. /*
  148. * Orion5x identification is done through PCIE space.
  149. */
  150. u32 orion5x_device_id(void)
  151. {
  152. return readl(PCIE_DEV_ID_OFF) >> 16;
  153. }
  154. u32 orion5x_device_rev(void)
  155. {
  156. return readl(PCIE_DEV_REV_OFF) & 0xff;
  157. }
  158. #if defined(CONFIG_DISPLAY_CPUINFO)
  159. /* Display device and revision IDs.
  160. * This function must cover all known device/revision
  161. * combinations, not only the one for which u-boot is
  162. * compiled; this way, one can identify actual HW in
  163. * case of a mismatch.
  164. */
  165. int print_cpuinfo(void)
  166. {
  167. char dev_str[7]; /* room enough for 0x0000 plus null byte */
  168. char rev_str[5]; /* room enough for 0x00 plus null byte */
  169. char *dev_name = NULL;
  170. char *rev_name = NULL;
  171. u32 dev = orion5x_device_id();
  172. u32 rev = orion5x_device_rev();
  173. if (dev == MV88F5181_DEV_ID) {
  174. dev_name = "MV88F5181";
  175. if (rev == MV88F5181_REV_B1)
  176. rev_name = "B1";
  177. else if (rev == MV88F5181L_REV_A1) {
  178. dev_name = "MV88F5181L";
  179. rev_name = "A1";
  180. } else if (rev == MV88F5181L_REV_A0) {
  181. dev_name = "MV88F5181L";
  182. rev_name = "A0";
  183. }
  184. } else if (dev == MV88F5182_DEV_ID) {
  185. dev_name = "MV88F5182";
  186. if (rev == MV88F5182_REV_A2)
  187. rev_name = "A2";
  188. } else if (dev == MV88F5281_DEV_ID) {
  189. dev_name = "MV88F5281";
  190. if (rev == MV88F5281_REV_D2)
  191. rev_name = "D2";
  192. else if (rev == MV88F5281_REV_D1)
  193. rev_name = "D1";
  194. else if (rev == MV88F5281_REV_D0)
  195. rev_name = "D0";
  196. } else if (dev == MV88F6183_DEV_ID) {
  197. dev_name = "MV88F6183";
  198. if (rev == MV88F6183_REV_B0)
  199. rev_name = "B0";
  200. }
  201. if (dev_name == NULL) {
  202. sprintf(dev_str, "0x%04x", dev);
  203. dev_name = dev_str;
  204. }
  205. if (rev_name == NULL) {
  206. sprintf(rev_str, "0x%02x", rev);
  207. rev_name = rev_str;
  208. }
  209. printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
  210. return 0;
  211. }
  212. #endif /* CONFIG_DISPLAY_CPUINFO */
  213. #ifdef CONFIG_ARCH_CPU_INIT
  214. int arch_cpu_init(void)
  215. {
  216. /* Enable and invalidate L2 cache in write through mode */
  217. invalidate_l2_cache();
  218. #ifdef CONFIG_SPL_BUILD
  219. orion5x_config_adr_windows();
  220. #endif
  221. return 0;
  222. }
  223. #endif /* CONFIG_ARCH_CPU_INIT */
  224. /*
  225. * SOC specific misc init
  226. */
  227. #if defined(CONFIG_ARCH_MISC_INIT)
  228. int arch_misc_init(void)
  229. {
  230. u32 temp;
  231. /*CPU streaming & write allocate */
  232. temp = readfr_extra_feature_reg();
  233. temp &= ~(1 << 28); /* disable wr alloc */
  234. writefr_extra_feature_reg(temp);
  235. temp = readfr_extra_feature_reg();
  236. temp &= ~(1 << 29); /* streaming disabled */
  237. writefr_extra_feature_reg(temp);
  238. /* L2Cache settings */
  239. temp = readfr_extra_feature_reg();
  240. /* Disable L2C pre fetch - Set bit 24 */
  241. temp |= (1 << 24);
  242. /* enable L2C - Set bit 22 */
  243. temp |= (1 << 22);
  244. writefr_extra_feature_reg(temp);
  245. icache_enable();
  246. /* Change reset vector to address 0x0 */
  247. temp = get_cr();
  248. set_cr(temp & ~CR_V);
  249. /* Set CPIOs and MPPs - values provided by board
  250. include file */
  251. writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
  252. writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
  253. writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
  254. writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
  255. writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
  256. writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
  257. /* initialize timer */
  258. timer_init_r();
  259. return 0;
  260. }
  261. #endif /* CONFIG_ARCH_MISC_INIT */
  262. #ifdef CONFIG_MVGBE
  263. int cpu_eth_init(struct bd_info *bis)
  264. {
  265. mvgbe_initialize(bis);
  266. return 0;
  267. }
  268. #endif