sdram.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Timing and Organization details of the ddr device parts used in OMAP5
  4. * EVM
  5. *
  6. * (C) Copyright 2010
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Aneesh V <aneesh@ti.com>
  10. * Sricharan R <r.sricharan@ti.com>
  11. */
  12. #include <common.h>
  13. #include <asm/emif.h>
  14. #include <asm/arch/sys_proto.h>
  15. /*
  16. * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  17. * EVM. Since the parts used and geometry are identical for
  18. * evm for a given OMAP5 revision, this information is kept
  19. * here instead of being in board directory. However the key functions
  20. * exported are weakly linked so that they can be over-ridden in the board
  21. * directory if there is a OMAP5 board in the future that uses a different
  22. * memory device or geometry.
  23. *
  24. * For any new board with different memory devices over-ride one or more
  25. * of the following functions as per the CONFIG flags you intend to enable:
  26. * - emif_get_reg_dump()
  27. * - emif_get_dmm_regs()
  28. * - emif_get_device_details()
  29. * - emif_get_device_timings()
  30. */
  31. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  32. const struct emif_regs emif_regs_532_mhz_2cs = {
  33. .sdram_config_init = 0x80800EBA,
  34. .sdram_config = 0x808022BA,
  35. .ref_ctrl = 0x0000081A,
  36. .sdram_tim1 = 0x772F6873,
  37. .sdram_tim2 = 0x304a129a,
  38. .sdram_tim3 = 0x02f7e45f,
  39. .read_idle_ctrl = 0x00050000,
  40. .zq_config = 0x000b3215,
  41. .temp_alert_config = 0x08000a05,
  42. .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
  43. .emif_ddr_phy_ctlr_1 = 0x0E28420d,
  44. .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
  45. .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
  46. .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
  47. .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
  48. .emif_ddr_ext_phy_ctrl_5 = 0x04010040
  49. };
  50. const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  51. .sdram_config_init = 0x80800EBA,
  52. .sdram_config = 0x808022BA,
  53. .ref_ctrl = 0x0000081A,
  54. .sdram_tim1 = 0x772F6873,
  55. .sdram_tim2 = 0x304a129a,
  56. .sdram_tim3 = 0x02f7e45f,
  57. .read_idle_ctrl = 0x00050000,
  58. .zq_config = 0x100b3215,
  59. .temp_alert_config = 0x08000a05,
  60. .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
  61. .emif_ddr_phy_ctlr_1 = 0x0E30400d,
  62. .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
  63. .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
  64. .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
  65. .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
  66. .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
  67. };
  68. const struct emif_regs emif_regs_266_mhz_2cs = {
  69. .sdram_config_init = 0x80800EBA,
  70. .sdram_config = 0x808022BA,
  71. .ref_ctrl = 0x0000040D,
  72. .sdram_tim1 = 0x2A86B419,
  73. .sdram_tim2 = 0x1025094A,
  74. .sdram_tim3 = 0x026BA22F,
  75. .read_idle_ctrl = 0x00050000,
  76. .zq_config = 0x000b3215,
  77. .temp_alert_config = 0x08000a05,
  78. .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
  79. .emif_ddr_phy_ctlr_1 = 0x0E28420d,
  80. .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
  81. .emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
  82. .emif_ddr_ext_phy_ctrl_3 = 0x14829052,
  83. .emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
  84. .emif_ddr_ext_phy_ctrl_5 = 0x04010040
  85. };
  86. const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  87. .sdram_config_init = 0x61851B32,
  88. .sdram_config = 0x61851B32,
  89. .sdram_config2 = 0x0,
  90. .ref_ctrl = 0x00001035,
  91. .sdram_tim1 = 0xCCCF36B3,
  92. .sdram_tim2 = 0x308F7FDA,
  93. .sdram_tim3 = 0x027F88A8,
  94. .read_idle_ctrl = 0x00050000,
  95. .zq_config = 0x0007190B,
  96. .temp_alert_config = 0x00000000,
  97. .emif_ddr_phy_ctlr_1_init = 0x0020420A,
  98. .emif_ddr_phy_ctlr_1 = 0x0024420A,
  99. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  100. .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
  101. .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
  102. .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
  103. .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
  104. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  105. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  106. .emif_rd_wr_lvl_ctl = 0x00000000,
  107. .emif_rd_wr_exec_thresh = 0x00000305
  108. };
  109. const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
  110. .sdram_config_init = 0x61851B32,
  111. .sdram_config = 0x61851B32,
  112. .sdram_config2 = 0x0,
  113. .ref_ctrl = 0x00001035,
  114. .sdram_tim1 = 0xCCCF36B3,
  115. .sdram_tim2 = 0x308F7FDA,
  116. .sdram_tim3 = 0x027F88A8,
  117. .read_idle_ctrl = 0x00050000,
  118. .zq_config = 0x1007190B,
  119. .temp_alert_config = 0x00000000,
  120. .emif_ddr_phy_ctlr_1_init = 0x0030400A,
  121. .emif_ddr_phy_ctlr_1 = 0x0034400A,
  122. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  123. .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
  124. .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
  125. .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
  126. .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
  127. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  128. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  129. .emif_rd_wr_lvl_ctl = 0x00000000,
  130. .emif_rd_wr_exec_thresh = 0x40000305
  131. };
  132. const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
  133. .dmm_lisa_map_0 = 0x0,
  134. .dmm_lisa_map_1 = 0x0,
  135. .dmm_lisa_map_2 = 0x80740300,
  136. .dmm_lisa_map_3 = 0xFF020100,
  137. .is_ma_present = 0x1
  138. };
  139. static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
  140. {
  141. switch (omap_revision()) {
  142. case OMAP5430_ES1_0:
  143. *regs = &emif_regs_532_mhz_2cs;
  144. break;
  145. case OMAP5432_ES1_0:
  146. *regs = &emif_regs_ddr3_532_mhz_1cs;
  147. break;
  148. case OMAP5430_ES2_0:
  149. *regs = &emif_regs_532_mhz_2cs_es2;
  150. break;
  151. case OMAP5432_ES2_0:
  152. default:
  153. *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
  154. break;
  155. }
  156. }
  157. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  158. __attribute__((weak, alias("emif_get_reg_dump_sdp")));
  159. static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
  160. **dmm_lisa_regs)
  161. {
  162. switch (omap_revision()) {
  163. case OMAP5430_ES1_0:
  164. case OMAP5430_ES2_0:
  165. case OMAP5432_ES1_0:
  166. case OMAP5432_ES2_0:
  167. default:
  168. *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
  169. break;
  170. }
  171. }
  172. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  173. __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
  174. #else
  175. static const struct lpddr2_device_details dev_4G_S4_details = {
  176. .type = LPDDR2_TYPE_S4,
  177. .density = LPDDR2_DENSITY_4Gb,
  178. .io_width = LPDDR2_IO_WIDTH_32,
  179. .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
  180. };
  181. static void emif_get_device_details_sdp(u32 emif_nr,
  182. struct lpddr2_device_details *cs0_device_details,
  183. struct lpddr2_device_details *cs1_device_details)
  184. {
  185. /* EMIF1 & EMIF2 have identical configuration */
  186. *cs0_device_details = dev_4G_S4_details;
  187. *cs1_device_details = dev_4G_S4_details;
  188. }
  189. void emif_get_device_details(u32 emif_nr,
  190. struct lpddr2_device_details *cs0_device_details,
  191. struct lpddr2_device_details *cs1_device_details)
  192. __attribute__((weak, alias("emif_get_device_details_sdp")));
  193. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  194. const u32 ext_phy_ctrl_const_base[] = {
  195. 0x01004010,
  196. 0x00001004,
  197. 0x04010040,
  198. 0x01004010,
  199. 0x00001004,
  200. 0x00000000,
  201. 0x00000000,
  202. 0x00000000,
  203. 0x80080080,
  204. 0x00800800,
  205. 0x08102040,
  206. 0x00000001,
  207. 0x540A8150,
  208. 0xA81502a0,
  209. 0x002A0540,
  210. 0x00000000,
  211. 0x00000000,
  212. 0x00000000,
  213. 0x00000077,
  214. 0x0
  215. };
  216. const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
  217. 0x01004010,
  218. 0x00001004,
  219. 0x04010040,
  220. 0x01004010,
  221. 0x00001004,
  222. 0x00000000,
  223. 0x00000000,
  224. 0x00000000,
  225. 0x80080080,
  226. 0x00800800,
  227. 0x08102040,
  228. 0x00000002,
  229. 0x0,
  230. 0x0,
  231. 0x0,
  232. 0x00000000,
  233. 0x00000000,
  234. 0x00000000,
  235. 0x00000057,
  236. 0x0
  237. };
  238. const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
  239. 0x50D4350D,
  240. 0x00000D43,
  241. 0x04010040,
  242. 0x01004010,
  243. 0x00001004,
  244. 0x00000000,
  245. 0x00000000,
  246. 0x00000000,
  247. 0x80080080,
  248. 0x00800800,
  249. 0x08102040,
  250. 0x00000002,
  251. 0x00000000,
  252. 0x00000000,
  253. 0x00000000,
  254. 0x00000000,
  255. 0x00000000,
  256. 0x00000000,
  257. 0x00000057,
  258. 0x0
  259. };
  260. /* Ext phy ctrl 1-35 regs */
  261. const u32
  262. dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
  263. 0x10040100,
  264. 0x00910091,
  265. 0x00950095,
  266. 0x009B009B,
  267. 0x009E009E,
  268. 0x00980098,
  269. 0x00340034,
  270. 0x00350035,
  271. 0x00340034,
  272. 0x00310031,
  273. 0x00340034,
  274. 0x007F007F,
  275. 0x007F007F,
  276. 0x007F007F,
  277. 0x007F007F,
  278. 0x007F007F,
  279. 0x00480048,
  280. 0x004A004A,
  281. 0x00520052,
  282. 0x00550055,
  283. 0x00500050,
  284. 0x00000000,
  285. 0x00600020,
  286. 0x40011080,
  287. 0x08102040,
  288. 0x0,
  289. 0x0,
  290. 0x0,
  291. 0x0,
  292. 0x0,
  293. 0x0,
  294. 0x0,
  295. 0x0,
  296. 0x0,
  297. 0x0
  298. };
  299. /* Ext phy ctrl 1-35 regs */
  300. const u32
  301. dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
  302. 0x10040100,
  303. 0x00910091,
  304. 0x00950095,
  305. 0x009B009B,
  306. 0x009E009E,
  307. 0x00980098,
  308. 0x00330033,
  309. 0x00330033,
  310. 0x002F002F,
  311. 0x00320032,
  312. 0x00310031,
  313. 0x007F007F,
  314. 0x007F007F,
  315. 0x007F007F,
  316. 0x007F007F,
  317. 0x007F007F,
  318. 0x00520052,
  319. 0x00520052,
  320. 0x00470047,
  321. 0x00490049,
  322. 0x00500050,
  323. 0x00000000,
  324. 0x00600020,
  325. 0x40011080,
  326. 0x08102040,
  327. 0x0,
  328. 0x0,
  329. 0x0,
  330. 0x0,
  331. 0x0,
  332. 0x0,
  333. 0x0,
  334. 0x0,
  335. 0x0,
  336. 0x0
  337. };
  338. /* Ext phy ctrl 1-35 regs */
  339. const u32
  340. dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
  341. 0x10040100,
  342. 0x00A400A4,
  343. 0x00A900A9,
  344. 0x00B000B0,
  345. 0x00B000B0,
  346. 0x00A400A4,
  347. 0x00390039,
  348. 0x00320032,
  349. 0x00320032,
  350. 0x00320032,
  351. 0x00440044,
  352. 0x00550055,
  353. 0x00550055,
  354. 0x00550055,
  355. 0x00550055,
  356. 0x007F007F,
  357. 0x004D004D,
  358. 0x00430043,
  359. 0x00560056,
  360. 0x00540054,
  361. 0x00600060,
  362. 0x0,
  363. 0x00600020,
  364. 0x40010080,
  365. 0x08102040,
  366. 0x0,
  367. 0x0,
  368. 0x0,
  369. 0x0,
  370. 0x0,
  371. 0x0,
  372. 0x0,
  373. 0x0,
  374. 0x0,
  375. 0x0
  376. };
  377. const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
  378. 0x04040100,
  379. 0x006B009F,
  380. 0x006B00A2,
  381. 0x006B00A8,
  382. 0x006B00A8,
  383. 0x006B00B2,
  384. 0x002F002F,
  385. 0x002F002F,
  386. 0x002F002F,
  387. 0x002F002F,
  388. 0x002F002F,
  389. 0x00600073,
  390. 0x00600071,
  391. 0x0060007C,
  392. 0x0060007E,
  393. 0x00600084,
  394. 0x00400053,
  395. 0x00400051,
  396. 0x0040005C,
  397. 0x0040005E,
  398. 0x00400064,
  399. 0x00800080,
  400. 0x00800080,
  401. 0x40010080,
  402. 0x08102040,
  403. 0x005B008F,
  404. 0x005B0092,
  405. 0x005B0098,
  406. 0x005B0098,
  407. 0x005B00A2,
  408. 0x00300043,
  409. 0x00300041,
  410. 0x0030004C,
  411. 0x0030004E,
  412. 0x00300054,
  413. 0x00000077
  414. };
  415. const struct lpddr2_mr_regs mr_regs = {
  416. .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
  417. .mr2 = 0x6,
  418. .mr3 = 0x1,
  419. .mr10 = MR10_ZQ_ZQINIT,
  420. .mr16 = MR16_REF_FULL_ARRAY
  421. };
  422. void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
  423. const u32 **regs,
  424. u32 *size)
  425. {
  426. switch (omap_revision()) {
  427. case OMAP5430_ES1_0:
  428. case OMAP5430_ES2_0:
  429. *regs = ext_phy_ctrl_const_base;
  430. *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
  431. break;
  432. case OMAP5432_ES1_0:
  433. *regs = ddr3_ext_phy_ctrl_const_base_es1;
  434. *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
  435. break;
  436. case OMAP5432_ES2_0:
  437. *regs = ddr3_ext_phy_ctrl_const_base_es2;
  438. *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
  439. break;
  440. case DRA752_ES1_0:
  441. case DRA752_ES1_1:
  442. case DRA752_ES2_0:
  443. if (emif_nr == 1) {
  444. *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
  445. *size =
  446. ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
  447. } else {
  448. *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
  449. *size =
  450. ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
  451. }
  452. break;
  453. case DRA722_ES1_0:
  454. *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
  455. *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
  456. break;
  457. case DRA762_ES1_0:
  458. case DRA762_ABZ_ES1_0:
  459. case DRA762_ACD_ES1_0:
  460. case DRA722_ES2_0:
  461. case DRA722_ES2_1:
  462. *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
  463. *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
  464. break;
  465. default:
  466. *regs = ddr3_ext_phy_ctrl_const_base_es2;
  467. *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
  468. }
  469. }
  470. void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
  471. {
  472. *regs = &mr_regs;
  473. }
  474. static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
  475. {
  476. u32 *ext_phy_ctrl_base = 0;
  477. u32 *emif_ext_phy_ctrl_base = 0;
  478. u32 emif_nr;
  479. const u32 *ext_phy_ctrl_const_regs;
  480. u32 i = 0;
  481. u32 size;
  482. emif_nr = (base == EMIF1_BASE) ? 1 : 2;
  483. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  484. ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
  485. emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
  486. /* Configure external phy control timing registers */
  487. for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
  488. writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
  489. /* Update shadow registers */
  490. writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
  491. }
  492. /*
  493. * external phy 6-24 registers do not change with
  494. * ddr frequency
  495. */
  496. emif_get_ext_phy_ctrl_const_regs(emif_nr,
  497. &ext_phy_ctrl_const_regs, &size);
  498. for (i = 0; i < size; i++) {
  499. writel(ext_phy_ctrl_const_regs[i],
  500. emif_ext_phy_ctrl_base++);
  501. /* Update shadow registers */
  502. writel(ext_phy_ctrl_const_regs[i],
  503. emif_ext_phy_ctrl_base++);
  504. }
  505. }
  506. static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
  507. {
  508. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  509. u32 *emif_ext_phy_ctrl_base = 0;
  510. u32 emif_nr;
  511. const u32 *ext_phy_ctrl_const_regs;
  512. u32 i, hw_leveling, size, phy;
  513. emif_nr = (base == EMIF1_BASE) ? 1 : 2;
  514. hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
  515. phy = regs->emif_ddr_phy_ctlr_1_init;
  516. emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
  517. emif_get_ext_phy_ctrl_const_regs(emif_nr,
  518. &ext_phy_ctrl_const_regs, &size);
  519. writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
  520. writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
  521. /*
  522. * Copy the predefined PHY register values
  523. * if leveling is disabled.
  524. */
  525. if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
  526. for (i = 1; i < 6; i++) {
  527. writel(ext_phy_ctrl_const_regs[i],
  528. &emif_ext_phy_ctrl_base[i * 2]);
  529. writel(ext_phy_ctrl_const_regs[i],
  530. &emif_ext_phy_ctrl_base[i * 2 + 1]);
  531. }
  532. if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
  533. for (i = 6; i < 11; i++) {
  534. writel(ext_phy_ctrl_const_regs[i],
  535. &emif_ext_phy_ctrl_base[i * 2]);
  536. writel(ext_phy_ctrl_const_regs[i],
  537. &emif_ext_phy_ctrl_base[i * 2 + 1]);
  538. }
  539. if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
  540. for (i = 11; i < 25; i++) {
  541. writel(ext_phy_ctrl_const_regs[i],
  542. &emif_ext_phy_ctrl_base[i * 2]);
  543. writel(ext_phy_ctrl_const_regs[i],
  544. &emif_ext_phy_ctrl_base[i * 2 + 1]);
  545. }
  546. if (hw_leveling) {
  547. /*
  548. * Write the init value for HW levling to occur
  549. */
  550. for (i = 21; i < 35; i++) {
  551. writel(ext_phy_ctrl_const_regs[i],
  552. &emif_ext_phy_ctrl_base[i * 2]);
  553. writel(ext_phy_ctrl_const_regs[i],
  554. &emif_ext_phy_ctrl_base[i * 2 + 1]);
  555. }
  556. }
  557. }
  558. void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
  559. {
  560. if (is_omap54xx())
  561. do_ext_phy_settings_omap5(base, regs);
  562. else
  563. do_ext_phy_settings_dra7(base, regs);
  564. }
  565. #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  566. static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
  567. .max_freq = 532000000,
  568. .RL = 8,
  569. .tRPab = 21,
  570. .tRCD = 18,
  571. .tWR = 15,
  572. .tRASmin = 42,
  573. .tRRD = 10,
  574. .tWTRx2 = 15,
  575. .tXSR = 140,
  576. .tXPx2 = 15,
  577. .tRFCab = 130,
  578. .tRTPx2 = 15,
  579. .tCKE = 3,
  580. .tCKESR = 15,
  581. .tZQCS = 90,
  582. .tZQCL = 360,
  583. .tZQINIT = 1000,
  584. .tDQSCKMAXx2 = 11,
  585. .tRASmax = 70,
  586. .tFAW = 50
  587. };
  588. static const struct lpddr2_min_tck min_tck = {
  589. .tRL = 3,
  590. .tRP_AB = 3,
  591. .tRCD = 3,
  592. .tWR = 3,
  593. .tRAS_MIN = 3,
  594. .tRRD = 2,
  595. .tWTR = 2,
  596. .tXP = 2,
  597. .tRTP = 2,
  598. .tCKE = 3,
  599. .tCKESR = 3,
  600. .tFAW = 8
  601. };
  602. static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
  603. &timings_jedec_532_mhz
  604. };
  605. static const struct lpddr2_device_timings dev_4G_S4_timings = {
  606. .ac_timings = ac_timings,
  607. .min_tck = &min_tck,
  608. };
  609. /*
  610. * List of status registers to be controlled back to control registers
  611. * after initial leveling
  612. * readreg, writereg
  613. */
  614. const struct read_write_regs omap5_bug_00339_regs[] = {
  615. { 8, 5 },
  616. { 9, 6 },
  617. { 10, 7 },
  618. { 14, 8 },
  619. { 15, 9 },
  620. { 16, 10 },
  621. { 11, 2 },
  622. { 12, 3 },
  623. { 13, 4 },
  624. { 17, 11 },
  625. { 18, 12 },
  626. { 19, 13 },
  627. };
  628. const struct read_write_regs dra_bug_00339_regs[] = {
  629. { 7, 7 },
  630. { 8, 8 },
  631. { 9, 9 },
  632. { 10, 10 },
  633. { 11, 11 },
  634. { 12, 2 },
  635. { 13, 3 },
  636. { 14, 4 },
  637. { 15, 5 },
  638. { 16, 6 },
  639. { 17, 12 },
  640. { 18, 13 },
  641. { 19, 14 },
  642. { 20, 15 },
  643. { 21, 16 },
  644. { 22, 17 },
  645. { 23, 18 },
  646. { 24, 19 },
  647. { 25, 20 },
  648. { 26, 21}
  649. };
  650. const struct read_write_regs *get_bug_regs(u32 *iterations)
  651. {
  652. const struct read_write_regs *bug_00339_regs_ptr = NULL;
  653. switch (omap_revision()) {
  654. case OMAP5430_ES1_0:
  655. case OMAP5430_ES2_0:
  656. case OMAP5432_ES1_0:
  657. case OMAP5432_ES2_0:
  658. bug_00339_regs_ptr = omap5_bug_00339_regs;
  659. *iterations = sizeof(omap5_bug_00339_regs)/
  660. sizeof(omap5_bug_00339_regs[0]);
  661. break;
  662. case DRA762_ABZ_ES1_0:
  663. case DRA762_ACD_ES1_0:
  664. case DRA762_ES1_0:
  665. case DRA752_ES1_0:
  666. case DRA752_ES1_1:
  667. case DRA752_ES2_0:
  668. case DRA722_ES1_0:
  669. case DRA722_ES2_0:
  670. case DRA722_ES2_1:
  671. bug_00339_regs_ptr = dra_bug_00339_regs;
  672. *iterations = sizeof(dra_bug_00339_regs)/
  673. sizeof(dra_bug_00339_regs[0]);
  674. break;
  675. default:
  676. printf("\n Error: UnKnown SOC");
  677. }
  678. return bug_00339_regs_ptr;
  679. }
  680. void emif_get_device_timings_sdp(u32 emif_nr,
  681. const struct lpddr2_device_timings **cs0_device_timings,
  682. const struct lpddr2_device_timings **cs1_device_timings)
  683. {
  684. /* Identical devices on EMIF1 & EMIF2 */
  685. *cs0_device_timings = &dev_4G_S4_timings;
  686. *cs1_device_timings = &dev_4G_S4_timings;
  687. }
  688. void emif_get_device_timings(u32 emif_nr,
  689. const struct lpddr2_device_timings **cs0_device_timings,
  690. const struct lpddr2_device_timings **cs1_device_timings)
  691. __attribute__((weak, alias("emif_get_device_timings_sdp")));
  692. #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */