prcm-regs.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * HW regs data for OMAP5 Soc
  5. *
  6. * (C) Copyright 2013
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Sricharan R <r.sricharan@ti.com>
  10. */
  11. #include <asm/omap_common.h>
  12. #include <asm/io.h>
  13. struct prcm_regs const omap5_es1_prcm = {
  14. /* cm1.ckgen */
  15. .cm_clksel_core = 0x4a004100,
  16. .cm_clksel_abe = 0x4a004108,
  17. .cm_dll_ctrl = 0x4a004110,
  18. .cm_clkmode_dpll_core = 0x4a004120,
  19. .cm_idlest_dpll_core = 0x4a004124,
  20. .cm_autoidle_dpll_core = 0x4a004128,
  21. .cm_clksel_dpll_core = 0x4a00412c,
  22. .cm_div_m2_dpll_core = 0x4a004130,
  23. .cm_div_m3_dpll_core = 0x4a004134,
  24. .cm_div_h11_dpll_core = 0x4a004138,
  25. .cm_div_h12_dpll_core = 0x4a00413c,
  26. .cm_div_h13_dpll_core = 0x4a004140,
  27. .cm_div_h14_dpll_core = 0x4a004144,
  28. .cm_ssc_deltamstep_dpll_core = 0x4a004148,
  29. .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
  30. .cm_emu_override_dpll_core = 0x4a004150,
  31. .cm_div_h22_dpllcore = 0x4a004154,
  32. .cm_div_h23_dpll_core = 0x4a004158,
  33. .cm_clkmode_dpll_mpu = 0x4a004160,
  34. .cm_idlest_dpll_mpu = 0x4a004164,
  35. .cm_autoidle_dpll_mpu = 0x4a004168,
  36. .cm_clksel_dpll_mpu = 0x4a00416c,
  37. .cm_div_m2_dpll_mpu = 0x4a004170,
  38. .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
  39. .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
  40. .cm_bypclk_dpll_mpu = 0x4a00419c,
  41. .cm_clkmode_dpll_iva = 0x4a0041a0,
  42. .cm_idlest_dpll_iva = 0x4a0041a4,
  43. .cm_autoidle_dpll_iva = 0x4a0041a8,
  44. .cm_clksel_dpll_iva = 0x4a0041ac,
  45. .cm_div_h11_dpll_iva = 0x4a0041b8,
  46. .cm_div_h12_dpll_iva = 0x4a0041bc,
  47. .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
  48. .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
  49. .cm_bypclk_dpll_iva = 0x4a0041dc,
  50. .cm_clkmode_dpll_abe = 0x4a0041e0,
  51. .cm_idlest_dpll_abe = 0x4a0041e4,
  52. .cm_autoidle_dpll_abe = 0x4a0041e8,
  53. .cm_clksel_dpll_abe = 0x4a0041ec,
  54. .cm_div_m2_dpll_abe = 0x4a0041f0,
  55. .cm_div_m3_dpll_abe = 0x4a0041f4,
  56. .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
  57. .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
  58. .cm_clkmode_dpll_ddrphy = 0x4a004220,
  59. .cm_idlest_dpll_ddrphy = 0x4a004224,
  60. .cm_autoidle_dpll_ddrphy = 0x4a004228,
  61. .cm_clksel_dpll_ddrphy = 0x4a00422c,
  62. .cm_div_m2_dpll_ddrphy = 0x4a004230,
  63. .cm_div_h11_dpll_ddrphy = 0x4a004238,
  64. .cm_div_h12_dpll_ddrphy = 0x4a00423c,
  65. .cm_div_h13_dpll_ddrphy = 0x4a004240,
  66. .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
  67. .cm_shadow_freq_config1 = 0x4a004260,
  68. .cm_mpu_mpu_clkctrl = 0x4a004320,
  69. /* cm1.dsp */
  70. .cm_dsp_clkstctrl = 0x4a004400,
  71. .cm_dsp_dsp_clkctrl = 0x4a004420,
  72. /* cm1.abe */
  73. .cm1_abe_clkstctrl = 0x4a004500,
  74. .cm1_abe_l4abe_clkctrl = 0x4a004520,
  75. .cm1_abe_aess_clkctrl = 0x4a004528,
  76. .cm1_abe_pdm_clkctrl = 0x4a004530,
  77. .cm1_abe_dmic_clkctrl = 0x4a004538,
  78. .cm1_abe_mcasp_clkctrl = 0x4a004540,
  79. .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
  80. .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
  81. .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
  82. .cm1_abe_slimbus_clkctrl = 0x4a004560,
  83. .cm1_abe_timer5_clkctrl = 0x4a004568,
  84. .cm1_abe_timer6_clkctrl = 0x4a004570,
  85. .cm1_abe_timer7_clkctrl = 0x4a004578,
  86. .cm1_abe_timer8_clkctrl = 0x4a004580,
  87. .cm1_abe_wdt3_clkctrl = 0x4a004588,
  88. /* cm2.ckgen */
  89. .cm_clksel_mpu_m3_iss_root = 0x4a008100,
  90. .cm_clksel_usb_60mhz = 0x4a008104,
  91. .cm_scale_fclk = 0x4a008108,
  92. .cm_core_dvfs_perf1 = 0x4a008110,
  93. .cm_core_dvfs_perf2 = 0x4a008114,
  94. .cm_core_dvfs_perf3 = 0x4a008118,
  95. .cm_core_dvfs_perf4 = 0x4a00811c,
  96. .cm_core_dvfs_current = 0x4a008124,
  97. .cm_iva_dvfs_perf_tesla = 0x4a008128,
  98. .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
  99. .cm_iva_dvfs_perf_abe = 0x4a008130,
  100. .cm_iva_dvfs_current = 0x4a008138,
  101. .cm_clkmode_dpll_per = 0x4a008140,
  102. .cm_idlest_dpll_per = 0x4a008144,
  103. .cm_autoidle_dpll_per = 0x4a008148,
  104. .cm_clksel_dpll_per = 0x4a00814c,
  105. .cm_div_m2_dpll_per = 0x4a008150,
  106. .cm_div_m3_dpll_per = 0x4a008154,
  107. .cm_div_h11_dpll_per = 0x4a008158,
  108. .cm_div_h12_dpll_per = 0x4a00815c,
  109. .cm_div_h14_dpll_per = 0x4a008164,
  110. .cm_ssc_deltamstep_dpll_per = 0x4a008168,
  111. .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
  112. .cm_emu_override_dpll_per = 0x4a008170,
  113. .cm_clkmode_dpll_usb = 0x4a008180,
  114. .cm_idlest_dpll_usb = 0x4a008184,
  115. .cm_autoidle_dpll_usb = 0x4a008188,
  116. .cm_clksel_dpll_usb = 0x4a00818c,
  117. .cm_div_m2_dpll_usb = 0x4a008190,
  118. .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
  119. .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
  120. .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
  121. .cm_clkmode_dpll_unipro = 0x4a0081c0,
  122. .cm_idlest_dpll_unipro = 0x4a0081c4,
  123. .cm_autoidle_dpll_unipro = 0x4a0081c8,
  124. .cm_clksel_dpll_unipro = 0x4a0081cc,
  125. .cm_div_m2_dpll_unipro = 0x4a0081d0,
  126. .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
  127. .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
  128. /* cm2.core */
  129. .cm_coreaon_bandgap_clkctrl = 0x4a008648,
  130. .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
  131. .cm_l3_1_clkstctrl = 0x4a008700,
  132. .cm_l3_1_dynamicdep = 0x4a008708,
  133. .cm_l3_1_l3_1_clkctrl = 0x4a008720,
  134. .cm_l3_2_clkstctrl = 0x4a008800,
  135. .cm_l3_2_dynamicdep = 0x4a008808,
  136. .cm_l3_2_l3_2_clkctrl = 0x4a008820,
  137. .cm_l3_gpmc_clkctrl = 0x4a008828,
  138. .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
  139. .cm_mpu_m3_clkstctrl = 0x4a008900,
  140. .cm_mpu_m3_staticdep = 0x4a008904,
  141. .cm_mpu_m3_dynamicdep = 0x4a008908,
  142. .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
  143. .cm_sdma_clkstctrl = 0x4a008a00,
  144. .cm_sdma_staticdep = 0x4a008a04,
  145. .cm_sdma_dynamicdep = 0x4a008a08,
  146. .cm_sdma_sdma_clkctrl = 0x4a008a20,
  147. .cm_memif_clkstctrl = 0x4a008b00,
  148. .cm_memif_dmm_clkctrl = 0x4a008b20,
  149. .cm_memif_emif_fw_clkctrl = 0x4a008b28,
  150. .cm_memif_emif_1_clkctrl = 0x4a008b30,
  151. .cm_memif_emif_2_clkctrl = 0x4a008b38,
  152. .cm_memif_dll_clkctrl = 0x4a008b40,
  153. .cm_memif_emif_h1_clkctrl = 0x4a008b50,
  154. .cm_memif_emif_h2_clkctrl = 0x4a008b58,
  155. .cm_memif_dll_h_clkctrl = 0x4a008b60,
  156. .cm_c2c_clkstctrl = 0x4a008c00,
  157. .cm_c2c_staticdep = 0x4a008c04,
  158. .cm_c2c_dynamicdep = 0x4a008c08,
  159. .cm_c2c_sad2d_clkctrl = 0x4a008c20,
  160. .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
  161. .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
  162. .cm_l4cfg_clkstctrl = 0x4a008d00,
  163. .cm_l4cfg_dynamicdep = 0x4a008d08,
  164. .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
  165. .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
  166. .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
  167. .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
  168. .cm_l3instr_clkstctrl = 0x4a008e00,
  169. .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
  170. .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
  171. .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
  172. /* cm2.ivahd */
  173. .cm_ivahd_clkstctrl = 0x4a008f00,
  174. .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
  175. .cm_ivahd_sl2_clkctrl = 0x4a008f28,
  176. /* cm2.cam */
  177. .cm_cam_clkstctrl = 0x4a009000,
  178. .cm_cam_iss_clkctrl = 0x4a009020,
  179. .cm_cam_fdif_clkctrl = 0x4a009028,
  180. /* cm2.dss */
  181. .cm_dss_clkstctrl = 0x4a009100,
  182. .cm_dss_dss_clkctrl = 0x4a009120,
  183. /* cm2.sgx */
  184. .cm_sgx_clkstctrl = 0x4a009200,
  185. .cm_sgx_sgx_clkctrl = 0x4a009220,
  186. /* cm2.l3init */
  187. .cm_l3init_clkstctrl = 0x4a009300,
  188. .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
  189. .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
  190. .cm_l3init_hsi_clkctrl = 0x4a009338,
  191. .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
  192. .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
  193. .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
  194. .cm_l3init_p1500_clkctrl = 0x4a009378,
  195. .cm_l3init_sata_clkctrl = 0x4a009388,
  196. .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
  197. .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
  198. .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
  199. /* cm2.l4per */
  200. .cm_l4per_clkstctrl = 0x4a009400,
  201. .cm_l4per_dynamicdep = 0x4a009408,
  202. .cm_l4per_adc_clkctrl = 0x4a009420,
  203. .cm_l4per_gptimer10_clkctrl = 0x4a009428,
  204. .cm_l4per_gptimer11_clkctrl = 0x4a009430,
  205. .cm_l4per_gptimer2_clkctrl = 0x4a009438,
  206. .cm_l4per_gptimer3_clkctrl = 0x4a009440,
  207. .cm_l4per_gptimer4_clkctrl = 0x4a009448,
  208. .cm_l4per_gptimer9_clkctrl = 0x4a009450,
  209. .cm_l4per_elm_clkctrl = 0x4a009458,
  210. .cm_l4per_gpio2_clkctrl = 0x4a009460,
  211. .cm_l4per_gpio3_clkctrl = 0x4a009468,
  212. .cm_l4per_gpio4_clkctrl = 0x4a009470,
  213. .cm_l4per_gpio5_clkctrl = 0x4a009478,
  214. .cm_l4per_gpio6_clkctrl = 0x4a009480,
  215. .cm_l4per_hdq1w_clkctrl = 0x4a009488,
  216. .cm_l4per_hecc1_clkctrl = 0x4a009490,
  217. .cm_l4per_hecc2_clkctrl = 0x4a009498,
  218. .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
  219. .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
  220. .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
  221. .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
  222. .cm_l4per_l4per_clkctrl = 0x4a0094c0,
  223. .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
  224. .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
  225. .cm_l4per_mgate_clkctrl = 0x4a0094e8,
  226. .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
  227. .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
  228. .cm_l4per_mcspi3_clkctrl = 0x4a009500,
  229. .cm_l4per_mcspi4_clkctrl = 0x4a009508,
  230. .cm_l4per_gpio7_clkctrl = 0x4a009510,
  231. .cm_l4per_gpio8_clkctrl = 0x4a009518,
  232. .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
  233. .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
  234. .cm_l4per_msprohg_clkctrl = 0x4a009530,
  235. .cm_l4per_slimbus2_clkctrl = 0x4a009538,
  236. .cm_l4per_uart1_clkctrl = 0x4a009540,
  237. .cm_l4per_uart2_clkctrl = 0x4a009548,
  238. .cm_l4per_uart3_clkctrl = 0x4a009550,
  239. .cm_l4per_uart4_clkctrl = 0x4a009558,
  240. .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
  241. .cm_l4per_i2c5_clkctrl = 0x4a009568,
  242. .cm_l4per_uart5_clkctrl = 0x4a009570,
  243. .cm_l4per_uart6_clkctrl = 0x4a009578,
  244. .cm_l4sec_clkstctrl = 0x4a009580,
  245. .cm_l4sec_staticdep = 0x4a009584,
  246. .cm_l4sec_dynamicdep = 0x4a009588,
  247. .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
  248. .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
  249. .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
  250. .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
  251. .cm_l4sec_rng_clkctrl = 0x4a0095c0,
  252. .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
  253. .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
  254. /* l4 wkup regs */
  255. .cm_abe_pll_ref_clksel = 0x4ae0610c,
  256. .cm_sys_clksel = 0x4ae06110,
  257. .cm_wkup_clkstctrl = 0x4ae07800,
  258. .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
  259. .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
  260. .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
  261. .cm_wkup_gpio1_clkctrl = 0x4ae07838,
  262. .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
  263. .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
  264. .cm_wkup_synctimer_clkctrl = 0x4ae07850,
  265. .cm_wkup_usim_clkctrl = 0x4ae07858,
  266. .cm_wkup_sarram_clkctrl = 0x4ae07860,
  267. .cm_wkup_keyboard_clkctrl = 0x4ae07878,
  268. .cm_wkup_rtc_clkctrl = 0x4ae07880,
  269. .cm_wkup_bandgap_clkctrl = 0x4ae07888,
  270. .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
  271. .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
  272. .prm_rstctrl = 0x4ae07b00,
  273. .prm_rstst = 0x4ae07b04,
  274. .prm_rsttime = 0x4ae07b08,
  275. .prm_vc_val_bypass = 0x4ae07ba0,
  276. .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
  277. .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
  278. /* SCRM stuff, used by some boards */
  279. .scrm_auxclk0 = 0x4ae0a310,
  280. .scrm_auxclk1 = 0x4ae0a314,
  281. };
  282. struct omap_sys_ctrl_regs const omap5_ctrl = {
  283. .control_status = 0x4A002134,
  284. .control_std_fuse_die_id_0 = 0x4A002200,
  285. .control_std_fuse_die_id_1 = 0x4A002208,
  286. .control_std_fuse_die_id_2 = 0x4A00220C,
  287. .control_std_fuse_die_id_3 = 0x4A002210,
  288. .control_phy_power_usb = 0x4A002370,
  289. .control_phy_power_sata = 0x4A002374,
  290. .control_padconf_core_base = 0x4A002800,
  291. .control_paconf_global = 0x4A002DA0,
  292. .control_paconf_mode = 0x4A002DA4,
  293. .control_smart1io_padconf_0 = 0x4A002DA8,
  294. .control_smart1io_padconf_1 = 0x4A002DAC,
  295. .control_smart1io_padconf_2 = 0x4A002DB0,
  296. .control_smart2io_padconf_0 = 0x4A002DB4,
  297. .control_smart2io_padconf_1 = 0x4A002DB8,
  298. .control_smart2io_padconf_2 = 0x4A002DBC,
  299. .control_smart3io_padconf_0 = 0x4A002DC0,
  300. .control_smart3io_padconf_1 = 0x4A002DC4,
  301. .control_pbias = 0x4A002E00,
  302. .control_i2c_0 = 0x4A002E04,
  303. .control_camera_rx = 0x4A002E08,
  304. .control_hdmi_tx_phy = 0x4A002E0C,
  305. .control_uniportm = 0x4A002E10,
  306. .control_dsiphy = 0x4A002E14,
  307. .control_mcbsplp = 0x4A002E18,
  308. .control_usb2phycore = 0x4A002E1C,
  309. .control_hdmi_1 = 0x4A002E20,
  310. .control_hsi = 0x4A002E24,
  311. .control_ddr3ch1_0 = 0x4A002E30,
  312. .control_ddr3ch2_0 = 0x4A002E34,
  313. .control_ddrch1_0 = 0x4A002E38,
  314. .control_ddrch1_1 = 0x4A002E3C,
  315. .control_ddrch2_0 = 0x4A002E40,
  316. .control_ddrch2_1 = 0x4A002E44,
  317. .control_lpddr2ch1_0 = 0x4A002E48,
  318. .control_lpddr2ch1_1 = 0x4A002E4C,
  319. .control_ddrio_0 = 0x4A002E50,
  320. .control_ddrio_1 = 0x4A002E54,
  321. .control_ddrio_2 = 0x4A002E58,
  322. .control_hyst_1 = 0x4A002E5C,
  323. .control_usbb_hsic_control = 0x4A002E60,
  324. .control_c2c = 0x4A002E64,
  325. .control_core_control_spare_rw = 0x4A002E68,
  326. .control_core_control_spare_r = 0x4A002E6C,
  327. .control_core_control_spare_r_c0 = 0x4A002E70,
  328. .control_srcomp_north_side = 0x4A002E74,
  329. .control_srcomp_south_side = 0x4A002E78,
  330. .control_srcomp_east_side = 0x4A002E7C,
  331. .control_srcomp_west_side = 0x4A002E80,
  332. .control_srcomp_code_latch = 0x4A002E84,
  333. .control_port_emif1_sdram_config = 0x4AE0C110,
  334. .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
  335. .control_port_emif2_sdram_config = 0x4AE0C118,
  336. .control_emif1_sdram_config_ext = 0x4AE0C144,
  337. .control_emif2_sdram_config_ext = 0x4AE0C148,
  338. .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318,
  339. .control_wkup_ldovbb_mm_voltage_ctrl = 0x4AE0C314,
  340. .control_padconf_wkup_base = 0x4AE0C800,
  341. .control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
  342. .control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
  343. .control_padconf_mode = 0x4AE0CDA8,
  344. .control_xtal_oscillator = 0x4AE0CDAC,
  345. .control_i2c_2 = 0x4AE0CDB0,
  346. .control_ckobuffer = 0x4AE0CDB4,
  347. .control_wkup_control_spare_rw = 0x4AE0CDB8,
  348. .control_wkup_control_spare_r = 0x4AE0CDBC,
  349. .control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
  350. .control_srcomp_east_side_wkup = 0x4AE0CDC4,
  351. .control_efuse_1 = 0x4AE0CDC8,
  352. .control_efuse_2 = 0x4AE0CDCC,
  353. .control_efuse_3 = 0x4AE0CDD0,
  354. .control_efuse_4 = 0x4AE0CDD4,
  355. .control_efuse_5 = 0x4AE0CDD8,
  356. .control_efuse_6 = 0x4AE0CDDC,
  357. .control_efuse_7 = 0x4AE0CDE0,
  358. .control_efuse_8 = 0x4AE0CDE4,
  359. .control_efuse_9 = 0x4AE0CDE8,
  360. .control_efuse_10 = 0x4AE0CDEC,
  361. .control_efuse_11 = 0x4AE0CDF0,
  362. .control_efuse_12 = 0x4AE0CDF4,
  363. .control_efuse_13 = 0x4AE0CDF8,
  364. };
  365. struct omap_sys_ctrl_regs const dra7xx_ctrl = {
  366. .control_status = 0x4A002134,
  367. .control_phy_power_usb = 0x4A002370,
  368. .control_phy_power_sata = 0x4A002374,
  369. .ctrl_core_sma_sw_0 = 0x4A0023FC,
  370. .ctrl_core_sma_sw_1 = 0x4A002534,
  371. .control_core_mac_id_0_lo = 0x4A002514,
  372. .control_core_mac_id_0_hi = 0x4A002518,
  373. .control_core_mac_id_1_lo = 0x4A00251C,
  374. .control_core_mac_id_1_hi = 0x4A002520,
  375. .control_core_mmr_lock1 = 0x4A002540,
  376. .control_core_mmr_lock2 = 0x4A002544,
  377. .control_core_mmr_lock3 = 0x4A002548,
  378. .control_core_mmr_lock4 = 0x4A00254C,
  379. .control_core_mmr_lock5 = 0x4A002550,
  380. .control_core_control_io1 = 0x4A002554,
  381. .control_core_control_io2 = 0x4A002558,
  382. .control_paconf_global = 0x4A002DA0,
  383. .control_paconf_mode = 0x4A002DA4,
  384. .control_smart1io_padconf_0 = 0x4A002DA8,
  385. .control_smart1io_padconf_1 = 0x4A002DAC,
  386. .control_smart1io_padconf_2 = 0x4A002DB0,
  387. .control_smart2io_padconf_0 = 0x4A002DB4,
  388. .control_smart2io_padconf_1 = 0x4A002DB8,
  389. .control_smart2io_padconf_2 = 0x4A002DBC,
  390. .control_smart3io_padconf_0 = 0x4A002DC0,
  391. .control_smart3io_padconf_1 = 0x4A002DC4,
  392. .control_pbias = 0x4A002E00,
  393. .control_i2c_0 = 0x4A002E04,
  394. .control_camera_rx = 0x4A002E08,
  395. .control_hdmi_tx_phy = 0x4A002E0C,
  396. .control_uniportm = 0x4A002E10,
  397. .control_dsiphy = 0x4A002E14,
  398. .control_mcbsplp = 0x4A002E18,
  399. .control_usb2phycore = 0x4A002E1C,
  400. .control_hdmi_1 = 0x4A002E20,
  401. .control_hsi = 0x4A002E24,
  402. .control_ddr3ch1_0 = 0x4A002E30,
  403. .control_ddr3ch2_0 = 0x4A002E34,
  404. .control_ddrch1_0 = 0x4A002E38,
  405. .control_ddrch1_1 = 0x4A002E3C,
  406. .control_ddrch2_0 = 0x4A002E40,
  407. .control_ddrch2_1 = 0x4A002E44,
  408. .control_lpddr2ch1_0 = 0x4A002E48,
  409. .control_lpddr2ch1_1 = 0x4A002E4C,
  410. .control_ddrio_0 = 0x4A002E50,
  411. .control_ddrio_1 = 0x4A002E54,
  412. .control_ddrio_2 = 0x4A002E58,
  413. .control_hyst_1 = 0x4A002E5C,
  414. .control_usbb_hsic_control = 0x4A002E60,
  415. .control_c2c = 0x4A002E64,
  416. .control_core_control_spare_rw = 0x4A002E68,
  417. .control_core_control_spare_r = 0x4A002E6C,
  418. .control_core_control_spare_r_c0 = 0x4A002E70,
  419. .control_srcomp_north_side = 0x4A002E74,
  420. .control_srcomp_south_side = 0x4A002E78,
  421. .control_srcomp_east_side = 0x4A002E7C,
  422. .control_srcomp_west_side = 0x4A002E80,
  423. .control_srcomp_code_latch = 0x4A002E84,
  424. .control_ddr_control_ext_0 = 0x4A002E88,
  425. .control_padconf_core_base = 0x4A003400,
  426. .control_port_emif1_sdram_config = 0x4AE0C110,
  427. .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
  428. .control_port_emif2_sdram_config = 0x4AE0C118,
  429. .control_emif1_sdram_config_ext = 0x4AE0C144,
  430. .control_emif2_sdram_config_ext = 0x4AE0C148,
  431. .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158,
  432. .control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470,
  433. .control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C,
  434. .control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154,
  435. .control_std_fuse_die_id_0 = 0x4AE0C200,
  436. .control_std_fuse_die_id_1 = 0x4AE0C208,
  437. .control_std_fuse_die_id_2 = 0x4AE0C20C,
  438. .control_std_fuse_die_id_3 = 0x4AE0C210,
  439. .control_padconf_mode = 0x4AE0C5A0,
  440. .control_xtal_oscillator = 0x4AE0C5A4,
  441. .control_i2c_2 = 0x4AE0C5A8,
  442. .control_ckobuffer = 0x4AE0C5AC,
  443. .control_wkup_control_spare_rw = 0x4AE0C5B0,
  444. .control_wkup_control_spare_r = 0x4AE0C5B4,
  445. .control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
  446. .control_srcomp_east_side_wkup = 0x4AE0C5BC,
  447. .control_efuse_1 = 0x4AE0C5C8,
  448. .control_efuse_2 = 0x4AE0C5CC,
  449. .control_efuse_3 = 0x4AE0C5D0,
  450. .control_efuse_4 = 0x4AE0C5D4,
  451. .control_efuse_13 = 0x4AE0C5F0,
  452. .iodelay_config_base = 0x4844A000,
  453. };
  454. struct prcm_regs const omap5_es2_prcm = {
  455. /* cm1.ckgen */
  456. .cm_clksel_core = 0x4a004100,
  457. .cm_clksel_abe = 0x4a004108,
  458. .cm_dll_ctrl = 0x4a004110,
  459. .cm_clkmode_dpll_core = 0x4a004120,
  460. .cm_idlest_dpll_core = 0x4a004124,
  461. .cm_autoidle_dpll_core = 0x4a004128,
  462. .cm_clksel_dpll_core = 0x4a00412c,
  463. .cm_div_m2_dpll_core = 0x4a004130,
  464. .cm_div_m3_dpll_core = 0x4a004134,
  465. .cm_div_h11_dpll_core = 0x4a004138,
  466. .cm_div_h12_dpll_core = 0x4a00413c,
  467. .cm_div_h13_dpll_core = 0x4a004140,
  468. .cm_div_h14_dpll_core = 0x4a004144,
  469. .cm_ssc_deltamstep_dpll_core = 0x4a004148,
  470. .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
  471. .cm_div_h21_dpll_core = 0x4a004150,
  472. .cm_div_h22_dpllcore = 0x4a004154,
  473. .cm_div_h23_dpll_core = 0x4a004158,
  474. .cm_div_h24_dpll_core = 0x4a00415c,
  475. .cm_clkmode_dpll_mpu = 0x4a004160,
  476. .cm_idlest_dpll_mpu = 0x4a004164,
  477. .cm_autoidle_dpll_mpu = 0x4a004168,
  478. .cm_clksel_dpll_mpu = 0x4a00416c,
  479. .cm_div_m2_dpll_mpu = 0x4a004170,
  480. .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
  481. .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
  482. .cm_bypclk_dpll_mpu = 0x4a00419c,
  483. .cm_clkmode_dpll_iva = 0x4a0041a0,
  484. .cm_idlest_dpll_iva = 0x4a0041a4,
  485. .cm_autoidle_dpll_iva = 0x4a0041a8,
  486. .cm_clksel_dpll_iva = 0x4a0041ac,
  487. .cm_div_h11_dpll_iva = 0x4a0041b8,
  488. .cm_div_h12_dpll_iva = 0x4a0041bc,
  489. .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
  490. .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
  491. .cm_bypclk_dpll_iva = 0x4a0041dc,
  492. .cm_clkmode_dpll_abe = 0x4a0041e0,
  493. .cm_idlest_dpll_abe = 0x4a0041e4,
  494. .cm_autoidle_dpll_abe = 0x4a0041e8,
  495. .cm_clksel_dpll_abe = 0x4a0041ec,
  496. .cm_div_m2_dpll_abe = 0x4a0041f0,
  497. .cm_div_m3_dpll_abe = 0x4a0041f4,
  498. .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
  499. .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
  500. .cm_clkmode_dpll_ddrphy = 0x4a004220,
  501. .cm_idlest_dpll_ddrphy = 0x4a004224,
  502. .cm_autoidle_dpll_ddrphy = 0x4a004228,
  503. .cm_clksel_dpll_ddrphy = 0x4a00422c,
  504. .cm_div_m2_dpll_ddrphy = 0x4a004230,
  505. .cm_div_h11_dpll_ddrphy = 0x4a004238,
  506. .cm_div_h12_dpll_ddrphy = 0x4a00423c,
  507. .cm_div_h13_dpll_ddrphy = 0x4a004240,
  508. .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
  509. .cm_shadow_freq_config1 = 0x4a004260,
  510. .cm_mpu_mpu_clkctrl = 0x4a004320,
  511. /* cm1.dsp */
  512. .cm_dsp_clkstctrl = 0x4a004400,
  513. .cm_dsp_dsp_clkctrl = 0x4a004420,
  514. /* cm1.abe */
  515. .cm1_abe_clkstctrl = 0x4a004500,
  516. .cm1_abe_l4abe_clkctrl = 0x4a004520,
  517. .cm1_abe_aess_clkctrl = 0x4a004528,
  518. .cm1_abe_pdm_clkctrl = 0x4a004530,
  519. .cm1_abe_dmic_clkctrl = 0x4a004538,
  520. .cm1_abe_mcasp_clkctrl = 0x4a004540,
  521. .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
  522. .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
  523. .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
  524. .cm1_abe_slimbus_clkctrl = 0x4a004560,
  525. .cm1_abe_timer5_clkctrl = 0x4a004568,
  526. .cm1_abe_timer6_clkctrl = 0x4a004570,
  527. .cm1_abe_timer7_clkctrl = 0x4a004578,
  528. .cm1_abe_timer8_clkctrl = 0x4a004580,
  529. .cm1_abe_wdt3_clkctrl = 0x4a004588,
  530. /* cm2.ckgen */
  531. .cm_clksel_mpu_m3_iss_root = 0x4a008100,
  532. .cm_clksel_usb_60mhz = 0x4a008104,
  533. .cm_scale_fclk = 0x4a008108,
  534. .cm_core_dvfs_perf1 = 0x4a008110,
  535. .cm_core_dvfs_perf2 = 0x4a008114,
  536. .cm_core_dvfs_perf3 = 0x4a008118,
  537. .cm_core_dvfs_perf4 = 0x4a00811c,
  538. .cm_core_dvfs_current = 0x4a008124,
  539. .cm_iva_dvfs_perf_tesla = 0x4a008128,
  540. .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
  541. .cm_iva_dvfs_perf_abe = 0x4a008130,
  542. .cm_iva_dvfs_current = 0x4a008138,
  543. .cm_clkmode_dpll_per = 0x4a008140,
  544. .cm_idlest_dpll_per = 0x4a008144,
  545. .cm_autoidle_dpll_per = 0x4a008148,
  546. .cm_clksel_dpll_per = 0x4a00814c,
  547. .cm_div_m2_dpll_per = 0x4a008150,
  548. .cm_div_m3_dpll_per = 0x4a008154,
  549. .cm_div_h11_dpll_per = 0x4a008158,
  550. .cm_div_h12_dpll_per = 0x4a00815c,
  551. .cm_div_h13_dpll_per = 0x4a008160,
  552. .cm_div_h14_dpll_per = 0x4a008164,
  553. .cm_ssc_deltamstep_dpll_per = 0x4a008168,
  554. .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
  555. .cm_emu_override_dpll_per = 0x4a008170,
  556. .cm_clkmode_dpll_usb = 0x4a008180,
  557. .cm_idlest_dpll_usb = 0x4a008184,
  558. .cm_autoidle_dpll_usb = 0x4a008188,
  559. .cm_clksel_dpll_usb = 0x4a00818c,
  560. .cm_div_m2_dpll_usb = 0x4a008190,
  561. .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
  562. .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
  563. .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
  564. .cm_clkmode_dpll_unipro = 0x4a0081c0,
  565. .cm_idlest_dpll_unipro = 0x4a0081c4,
  566. .cm_autoidle_dpll_unipro = 0x4a0081c8,
  567. .cm_clksel_dpll_unipro = 0x4a0081cc,
  568. .cm_div_m2_dpll_unipro = 0x4a0081d0,
  569. .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
  570. .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
  571. .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640,
  572. .cm_coreaon_bandgap_clkctrl = 0x4a008648,
  573. .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
  574. /* cm2.core */
  575. .cm_l3_1_clkstctrl = 0x4a008700,
  576. .cm_l3_1_dynamicdep = 0x4a008708,
  577. .cm_l3_1_l3_1_clkctrl = 0x4a008720,
  578. .cm_l3_2_clkstctrl = 0x4a008800,
  579. .cm_l3_2_dynamicdep = 0x4a008808,
  580. .cm_l3_2_l3_2_clkctrl = 0x4a008820,
  581. .cm_l3_gpmc_clkctrl = 0x4a008828,
  582. .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
  583. .cm_mpu_m3_clkstctrl = 0x4a008900,
  584. .cm_mpu_m3_staticdep = 0x4a008904,
  585. .cm_mpu_m3_dynamicdep = 0x4a008908,
  586. .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
  587. .cm_sdma_clkstctrl = 0x4a008a00,
  588. .cm_sdma_staticdep = 0x4a008a04,
  589. .cm_sdma_dynamicdep = 0x4a008a08,
  590. .cm_sdma_sdma_clkctrl = 0x4a008a20,
  591. .cm_memif_clkstctrl = 0x4a008b00,
  592. .cm_memif_dmm_clkctrl = 0x4a008b20,
  593. .cm_memif_emif_fw_clkctrl = 0x4a008b28,
  594. .cm_memif_emif_1_clkctrl = 0x4a008b30,
  595. .cm_memif_emif_2_clkctrl = 0x4a008b38,
  596. .cm_memif_dll_clkctrl = 0x4a008b40,
  597. .cm_memif_emif_h1_clkctrl = 0x4a008b50,
  598. .cm_memif_emif_h2_clkctrl = 0x4a008b58,
  599. .cm_memif_dll_h_clkctrl = 0x4a008b60,
  600. .cm_c2c_clkstctrl = 0x4a008c00,
  601. .cm_c2c_staticdep = 0x4a008c04,
  602. .cm_c2c_dynamicdep = 0x4a008c08,
  603. .cm_c2c_sad2d_clkctrl = 0x4a008c20,
  604. .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
  605. .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
  606. .cm_l4cfg_clkstctrl = 0x4a008d00,
  607. .cm_l4cfg_dynamicdep = 0x4a008d08,
  608. .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
  609. .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
  610. .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
  611. .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
  612. .cm_l3instr_clkstctrl = 0x4a008e00,
  613. .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
  614. .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
  615. .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
  616. .cm_l4per_clkstctrl = 0x4a009000,
  617. .cm_l4per_dynamicdep = 0x4a009008,
  618. .cm_l4per_adc_clkctrl = 0x4a009020,
  619. .cm_l4per_gptimer10_clkctrl = 0x4a009028,
  620. .cm_l4per_gptimer11_clkctrl = 0x4a009030,
  621. .cm_l4per_gptimer2_clkctrl = 0x4a009038,
  622. .cm_l4per_gptimer3_clkctrl = 0x4a009040,
  623. .cm_l4per_gptimer4_clkctrl = 0x4a009048,
  624. .cm_l4per_gptimer9_clkctrl = 0x4a009050,
  625. .cm_l4per_elm_clkctrl = 0x4a009058,
  626. .cm_l4per_gpio2_clkctrl = 0x4a009060,
  627. .cm_l4per_gpio3_clkctrl = 0x4a009068,
  628. .cm_l4per_gpio4_clkctrl = 0x4a009070,
  629. .cm_l4per_gpio5_clkctrl = 0x4a009078,
  630. .cm_l4per_gpio6_clkctrl = 0x4a009080,
  631. .cm_l4per_hdq1w_clkctrl = 0x4a009088,
  632. .cm_l4per_hecc1_clkctrl = 0x4a009090,
  633. .cm_l4per_hecc2_clkctrl = 0x4a009098,
  634. .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
  635. .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
  636. .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
  637. .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
  638. .cm_l4per_l4per_clkctrl = 0x4a0090c0,
  639. .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
  640. .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
  641. .cm_l4per_mgate_clkctrl = 0x4a0090e8,
  642. .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
  643. .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
  644. .cm_l4per_mcspi3_clkctrl = 0x4a009100,
  645. .cm_l4per_mcspi4_clkctrl = 0x4a009108,
  646. .cm_l4per_gpio7_clkctrl = 0x4a009110,
  647. .cm_l4per_gpio8_clkctrl = 0x4a009118,
  648. .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
  649. .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
  650. .cm_l4per_msprohg_clkctrl = 0x4a009130,
  651. .cm_l4per_slimbus2_clkctrl = 0x4a009138,
  652. .cm_l4per_uart1_clkctrl = 0x4a009140,
  653. .cm_l4per_uart2_clkctrl = 0x4a009148,
  654. .cm_l4per_uart3_clkctrl = 0x4a009150,
  655. .cm_l4per_uart4_clkctrl = 0x4a009158,
  656. .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
  657. .cm_l4per_i2c5_clkctrl = 0x4a009168,
  658. .cm_l4per_uart5_clkctrl = 0x4a009170,
  659. .cm_l4per_uart6_clkctrl = 0x4a009178,
  660. .cm_l4sec_clkstctrl = 0x4a009180,
  661. .cm_l4sec_staticdep = 0x4a009184,
  662. .cm_l4sec_dynamicdep = 0x4a009188,
  663. .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
  664. .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
  665. .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
  666. .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
  667. .cm_l4sec_rng_clkctrl = 0x4a0091c0,
  668. .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
  669. .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
  670. /* cm2.ivahd */
  671. .cm_ivahd_clkstctrl = 0x4a009200,
  672. .cm_ivahd_ivahd_clkctrl = 0x4a009220,
  673. .cm_ivahd_sl2_clkctrl = 0x4a009228,
  674. /* cm2.cam */
  675. .cm_cam_clkstctrl = 0x4a009300,
  676. .cm_cam_iss_clkctrl = 0x4a009320,
  677. .cm_cam_fdif_clkctrl = 0x4a009328,
  678. /* cm2.dss */
  679. .cm_dss_clkstctrl = 0x4a009400,
  680. .cm_dss_dss_clkctrl = 0x4a009420,
  681. /* cm2.sgx */
  682. .cm_sgx_clkstctrl = 0x4a009500,
  683. .cm_sgx_sgx_clkctrl = 0x4a009520,
  684. /* cm2.l3init */
  685. .cm_l3init_clkstctrl = 0x4a009600,
  686. /* cm2.l3init */
  687. .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
  688. .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
  689. .cm_l3init_hsi_clkctrl = 0x4a009638,
  690. .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
  691. .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
  692. .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
  693. .cm_l3init_p1500_clkctrl = 0x4a009678,
  694. .cm_l3init_sata_clkctrl = 0x4a009688,
  695. .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
  696. .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
  697. .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
  698. .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
  699. /* prm irqstatus regs */
  700. .prm_irqstatus_mpu = 0x4ae06010,
  701. .prm_irqstatus_mpu_2 = 0x4ae06014,
  702. /* l4 wkup regs */
  703. .cm_abe_pll_ref_clksel = 0x4ae0610c,
  704. .cm_sys_clksel = 0x4ae06110,
  705. .cm_wkup_clkstctrl = 0x4ae07900,
  706. .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
  707. .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
  708. .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
  709. .cm_wkup_gpio1_clkctrl = 0x4ae07938,
  710. .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
  711. .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
  712. .cm_wkup_synctimer_clkctrl = 0x4ae07950,
  713. .cm_wkup_usim_clkctrl = 0x4ae07958,
  714. .cm_wkup_sarram_clkctrl = 0x4ae07960,
  715. .cm_wkup_keyboard_clkctrl = 0x4ae07978,
  716. .cm_wkup_rtc_clkctrl = 0x4ae07980,
  717. .cm_wkup_bandgap_clkctrl = 0x4ae07988,
  718. .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
  719. .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
  720. .prm_rstctrl = 0x4ae07c00,
  721. .prm_rstst = 0x4ae07c04,
  722. .prm_rsttime = 0x4ae07c08,
  723. .prm_vc_val_bypass = 0x4ae07ca0,
  724. .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
  725. .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
  726. .prm_abbldo_mpu_setup = 0x4ae07cdc,
  727. .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
  728. .prm_abbldo_mm_setup = 0x4ae07ce4,
  729. .prm_abbldo_mm_ctrl = 0x4ae07ce8,
  730. /* SCRM stuff, used by some boards */
  731. .scrm_auxclk0 = 0x4ae0a310,
  732. .scrm_auxclk1 = 0x4ae0a314,
  733. };
  734. struct prcm_regs const dra7xx_prcm = {
  735. /* cm1.ckgen */
  736. .cm_clksel_core = 0x4a005100,
  737. .cm_clksel_abe = 0x4a005108,
  738. .cm_dll_ctrl = 0x4a005110,
  739. .cm_clkmode_dpll_core = 0x4a005120,
  740. .cm_idlest_dpll_core = 0x4a005124,
  741. .cm_autoidle_dpll_core = 0x4a005128,
  742. .cm_clksel_dpll_core = 0x4a00512c,
  743. .cm_div_m2_dpll_core = 0x4a005130,
  744. .cm_div_m3_dpll_core = 0x4a005134,
  745. .cm_div_h11_dpll_core = 0x4a005138,
  746. .cm_div_h12_dpll_core = 0x4a00513c,
  747. .cm_div_h13_dpll_core = 0x4a005140,
  748. .cm_div_h14_dpll_core = 0x4a005144,
  749. .cm_ssc_deltamstep_dpll_core = 0x4a005148,
  750. .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
  751. .cm_div_h21_dpll_core = 0x4a005150,
  752. .cm_div_h22_dpllcore = 0x4a005154,
  753. .cm_div_h23_dpll_core = 0x4a005158,
  754. .cm_div_h24_dpll_core = 0x4a00515c,
  755. .cm_clkmode_dpll_mpu = 0x4a005160,
  756. .cm_idlest_dpll_mpu = 0x4a005164,
  757. .cm_autoidle_dpll_mpu = 0x4a005168,
  758. .cm_clksel_dpll_mpu = 0x4a00516c,
  759. .cm_div_m2_dpll_mpu = 0x4a005170,
  760. .cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
  761. .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
  762. .cm_bypclk_dpll_mpu = 0x4a00519c,
  763. .cm_clkmode_dpll_iva = 0x4a0051a0,
  764. .cm_idlest_dpll_iva = 0x4a0051a4,
  765. .cm_autoidle_dpll_iva = 0x4a0051a8,
  766. .cm_clksel_dpll_iva = 0x4a0051ac,
  767. .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
  768. .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
  769. .cm_bypclk_dpll_iva = 0x4a0051dc,
  770. .cm_clkmode_dpll_abe = 0x4a0051e0,
  771. .cm_idlest_dpll_abe = 0x4a0051e4,
  772. .cm_autoidle_dpll_abe = 0x4a0051e8,
  773. .cm_clksel_dpll_abe = 0x4a0051ec,
  774. .cm_div_m2_dpll_abe = 0x4a0051f0,
  775. .cm_div_m3_dpll_abe = 0x4a0051f4,
  776. .cm_ssc_deltamstep_dpll_abe = 0x4a005208,
  777. .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
  778. .cm_clkmode_dpll_ddrphy = 0x4a005210,
  779. .cm_idlest_dpll_ddrphy = 0x4a005214,
  780. .cm_autoidle_dpll_ddrphy = 0x4a005218,
  781. .cm_clksel_dpll_ddrphy = 0x4a00521c,
  782. .cm_div_m2_dpll_ddrphy = 0x4a005220,
  783. .cm_div_h11_dpll_ddrphy = 0x4a005228,
  784. .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
  785. .cm_clkmode_dpll_dsp = 0x4a005234,
  786. .cm_shadow_freq_config1 = 0x4a005260,
  787. .cm_clkmode_dpll_gmac = 0x4a0052a8,
  788. .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
  789. .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
  790. .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
  791. .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
  792. /* cm1.mpu */
  793. .cm_mpu_mpu_clkctrl = 0x4a005320,
  794. /* cm1.dsp */
  795. .cm_dsp_clkstctrl = 0x4a005400,
  796. .cm_dsp_dsp_clkctrl = 0x4a005420,
  797. /* cm IPU */
  798. .cm_ipu_clkstctrl = 0x4a005540,
  799. .cm_ipu_i2c5_clkctrl = 0x4a005578,
  800. /* prm irqstatus regs */
  801. .prm_irqstatus_mpu = 0x4ae06010,
  802. .prm_irqstatus_mpu_2 = 0x4ae06014,
  803. /* cm2.ckgen */
  804. .cm_clksel_usb_60mhz = 0x4a008104,
  805. .cm_clkmode_dpll_per = 0x4a008140,
  806. .cm_idlest_dpll_per = 0x4a008144,
  807. .cm_autoidle_dpll_per = 0x4a008148,
  808. .cm_clksel_dpll_per = 0x4a00814c,
  809. .cm_div_m2_dpll_per = 0x4a008150,
  810. .cm_div_m3_dpll_per = 0x4a008154,
  811. .cm_div_h11_dpll_per = 0x4a008158,
  812. .cm_div_h12_dpll_per = 0x4a00815c,
  813. .cm_div_h13_dpll_per = 0x4a008160,
  814. .cm_div_h14_dpll_per = 0x4a008164,
  815. .cm_ssc_deltamstep_dpll_per = 0x4a008168,
  816. .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
  817. .cm_clkmode_dpll_usb = 0x4a008180,
  818. .cm_idlest_dpll_usb = 0x4a008184,
  819. .cm_autoidle_dpll_usb = 0x4a008188,
  820. .cm_clksel_dpll_usb = 0x4a00818c,
  821. .cm_div_m2_dpll_usb = 0x4a008190,
  822. .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
  823. .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
  824. .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
  825. .cm_clkmode_dpll_pcie_ref = 0x4a008200,
  826. .cm_clkmode_apll_pcie = 0x4a00821c,
  827. .cm_idlest_apll_pcie = 0x4a008220,
  828. .cm_div_m2_apll_pcie = 0x4a008224,
  829. .cm_clkvcoldo_apll_pcie = 0x4a008228,
  830. /* cm2.core */
  831. .cm_l3_1_clkstctrl = 0x4a008700,
  832. .cm_l3_1_dynamicdep = 0x4a008708,
  833. .cm_l3_1_l3_1_clkctrl = 0x4a008720,
  834. .cm_l3_gpmc_clkctrl = 0x4a008728,
  835. .cm_mpu_m3_clkstctrl = 0x4a008900,
  836. .cm_mpu_m3_staticdep = 0x4a008904,
  837. .cm_mpu_m3_dynamicdep = 0x4a008908,
  838. .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
  839. .cm_sdma_clkstctrl = 0x4a008a00,
  840. .cm_sdma_staticdep = 0x4a008a04,
  841. .cm_sdma_dynamicdep = 0x4a008a08,
  842. .cm_sdma_sdma_clkctrl = 0x4a008a20,
  843. .cm_memif_clkstctrl = 0x4a008b00,
  844. .cm_memif_dmm_clkctrl = 0x4a008b20,
  845. .cm_memif_emif_fw_clkctrl = 0x4a008b28,
  846. .cm_memif_emif_1_clkctrl = 0x4a008b30,
  847. .cm_memif_emif_2_clkctrl = 0x4a008b38,
  848. .cm_memif_dll_clkctrl = 0x4a008b40,
  849. .cm_l4cfg_clkstctrl = 0x4a008d00,
  850. .cm_l4cfg_dynamicdep = 0x4a008d08,
  851. .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
  852. .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
  853. .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
  854. .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
  855. .cm_l3instr_clkstctrl = 0x4a008e00,
  856. .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
  857. .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
  858. .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
  859. /* cm2.ivahd */
  860. .cm_ivahd_clkstctrl = 0x4a008f00,
  861. .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
  862. .cm_ivahd_sl2_clkctrl = 0x4a008f28,
  863. /* cm2.cam */
  864. .cm_cam_clkstctrl = 0x4a009000,
  865. .cm_cam_vip1_clkctrl = 0x4a009020,
  866. .cm_cam_vip2_clkctrl = 0x4a009028,
  867. .cm_cam_vip3_clkctrl = 0x4a009030,
  868. .cm_cam_lvdsrx_clkctrl = 0x4a009038,
  869. .cm_cam_csi1_clkctrl = 0x4a009040,
  870. .cm_cam_csi2_clkctrl = 0x4a009048,
  871. /* cm2.dss */
  872. .cm_dss_clkstctrl = 0x4a009100,
  873. .cm_dss_dss_clkctrl = 0x4a009120,
  874. /* cm2.sgx */
  875. .cm_sgx_clkstctrl = 0x4a009200,
  876. .cm_sgx_sgx_clkctrl = 0x4a009220,
  877. /* cm2.l3init */
  878. .cm_l3init_clkstctrl = 0x4a009300,
  879. /* cm2.l3init */
  880. .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
  881. .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
  882. .cm_l3init_hsusbhost_clkctrl = 0x4a009340,
  883. .cm_l3init_hsusbotg_clkctrl = 0x4a009348,
  884. .cm_l3init_hsusbtll_clkctrl = 0x4a009350,
  885. .cm_l3init_sata_clkctrl = 0x4a009388,
  886. .cm_gmac_clkstctrl = 0x4a0093c0,
  887. .cm_gmac_gmac_clkctrl = 0x4a0093d0,
  888. .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
  889. .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
  890. .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0,
  891. .cm_l3init_usb_otg_ss2_clkctrl = 0x4a009340,
  892. /* cm2.l4per */
  893. .cm_l4per_clkstctrl = 0x4a009700,
  894. .cm_l4per_dynamicdep = 0x4a009708,
  895. .cm_l4per_gptimer10_clkctrl = 0x4a009728,
  896. .cm_l4per_gptimer11_clkctrl = 0x4a009730,
  897. .cm_l4per_gptimer2_clkctrl = 0x4a009738,
  898. .cm_l4per_gptimer3_clkctrl = 0x4a009740,
  899. .cm_l4per_gptimer4_clkctrl = 0x4a009748,
  900. .cm_l4per_gptimer9_clkctrl = 0x4a009750,
  901. .cm_l4per_elm_clkctrl = 0x4a009758,
  902. .cm_l4per_gpio2_clkctrl = 0x4a009760,
  903. .cm_l4per_gpio3_clkctrl = 0x4a009768,
  904. .cm_l4per_gpio4_clkctrl = 0x4a009770,
  905. .cm_l4per_gpio5_clkctrl = 0x4a009778,
  906. .cm_l4per_gpio6_clkctrl = 0x4a009780,
  907. .cm_l4per_hdq1w_clkctrl = 0x4a009788,
  908. .cm_l4per_i2c1_clkctrl = 0x4a0097a0,
  909. .cm_l4per_i2c2_clkctrl = 0x4a0097a8,
  910. .cm_l4per_i2c3_clkctrl = 0x4a0097b0,
  911. .cm_l4per_i2c4_clkctrl = 0x4a0097b8,
  912. .cm_l4per_l4per_clkctrl = 0x4a0097c0,
  913. .cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
  914. .cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
  915. .cm_l4per_mcspi3_clkctrl = 0x4a009800,
  916. .cm_l4per_mcspi4_clkctrl = 0x4a009808,
  917. .cm_l4per_gpio7_clkctrl = 0x4a009810,
  918. .cm_l4per_gpio8_clkctrl = 0x4a009818,
  919. .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
  920. .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
  921. .cm_l4per_qspi_clkctrl = 0x4a009838,
  922. .cm_l4per_uart1_clkctrl = 0x4a009840,
  923. .cm_l4per_uart2_clkctrl = 0x4a009848,
  924. .cm_l4per_uart3_clkctrl = 0x4a009850,
  925. .cm_l4per_uart4_clkctrl = 0x4a009858,
  926. .cm_l4per_uart5_clkctrl = 0x4a009870,
  927. .cm_l4sec_clkstctrl = 0x4a009880,
  928. .cm_l4sec_staticdep = 0x4a009884,
  929. .cm_l4sec_dynamicdep = 0x4a009888,
  930. .cm_l4sec_aes1_clkctrl = 0x4a0098a0,
  931. .cm_l4sec_aes2_clkctrl = 0x4a0098a8,
  932. .cm_l4sec_des3des_clkctrl = 0x4a0098b0,
  933. .cm_l4sec_rng_clkctrl = 0x4a0098c0,
  934. .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
  935. .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
  936. /* l4 wkup regs */
  937. .cm_abe_pll_ref_clksel = 0x4ae0610c,
  938. .cm_sys_clksel = 0x4ae06110,
  939. .cm_abe_pll_sys_clksel = 0x4ae06118,
  940. .cm_wkup_clkstctrl = 0x4ae07800,
  941. .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
  942. .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
  943. .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
  944. .cm_wkup_gpio1_clkctrl = 0x4ae07838,
  945. .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
  946. .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
  947. .cm_wkup_sarram_clkctrl = 0x4ae07860,
  948. .cm_wkup_keyboard_clkctrl = 0x4ae07878,
  949. .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
  950. .prm_rstctrl = 0x4ae07d00,
  951. .prm_rstst = 0x4ae07d04,
  952. .prm_rsttime = 0x4ae07d08,
  953. .prm_io_pmctrl = 0x4ae07d20,
  954. .prm_vc_val_bypass = 0x4ae07da0,
  955. .prm_vc_cfg_i2c_mode = 0x4ae07db4,
  956. .prm_vc_cfg_i2c_clk = 0x4ae07db8,
  957. .prm_abbldo_mpu_setup = 0x4AE07DDC,
  958. .prm_abbldo_mpu_ctrl = 0x4AE07DE0,
  959. .prm_abbldo_iva_setup = 0x4AE07E34,
  960. .prm_abbldo_iva_ctrl = 0x4AE07E24,
  961. .prm_abbldo_eve_setup = 0x4AE07E30,
  962. .prm_abbldo_eve_ctrl = 0x4AE07E20,
  963. .prm_abbldo_gpu_setup = 0x4AE07DE4,
  964. .prm_abbldo_gpu_ctrl = 0x4AE07DE8,
  965. /*l3main1 edma*/
  966. .cm_l3main1_tptc1_clkctrl = 0x4a008778,
  967. .cm_l3main1_tptc2_clkctrl = 0x4a008780,
  968. };
  969. void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
  970. {
  971. u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
  972. (*ctrl)->ctrl_core_sma_sw_0;
  973. clrsetbits_le32(reg, clear_bits, set_bits);
  974. }