fdt.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Texas Instruments, Inc.
  4. */
  5. #include <common.h>
  6. #include <hang.h>
  7. #include <log.h>
  8. #include <linux/libfdt.h>
  9. #include <fdt_support.h>
  10. #include <malloc.h>
  11. #include <asm/omap_common.h>
  12. #include <asm/arch-omap5/sys_proto.h>
  13. #ifdef CONFIG_TI_SECURE_DEVICE
  14. /* Give zero values if not already defined */
  15. #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
  16. #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
  17. #endif
  18. #ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
  19. #define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
  20. #endif
  21. static u32 hs_irq_skip[] = {
  22. 8, /* Secure violation reporting interrupt */
  23. 15, /* One interrupt for SDMA by secure world */
  24. 118 /* One interrupt for Crypto DMA by secure world */
  25. };
  26. static int ft_hs_fixup_crossbar(void *fdt, struct bd_info *bd)
  27. {
  28. const char *path;
  29. int offs;
  30. int ret;
  31. int len, i, old_cnt, new_cnt;
  32. u32 *temp;
  33. const u32 *p_data;
  34. /*
  35. * Increase the size of the fdt
  36. * so we have some breathing room
  37. */
  38. ret = fdt_increase_size(fdt, 512);
  39. if (ret < 0) {
  40. printf("Could not increase size of device tree: %s\n",
  41. fdt_strerror(ret));
  42. return ret;
  43. }
  44. /* Reserve IRQs that are used/needed by secure world */
  45. path = "/ocp/crossbar";
  46. offs = fdt_path_offset(fdt, path);
  47. if (offs < 0) {
  48. debug("Node %s not found.\n", path);
  49. return 0;
  50. }
  51. /* Get current entries */
  52. p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
  53. if (p_data)
  54. old_cnt = len / sizeof(u32);
  55. else
  56. old_cnt = 0;
  57. new_cnt = sizeof(hs_irq_skip) /
  58. sizeof(hs_irq_skip[0]);
  59. /* Create new/updated skip list for HS parts */
  60. temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
  61. for (i = 0; i < new_cnt; i++)
  62. temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
  63. for (i = 0; i < old_cnt; i++)
  64. temp[i + new_cnt] = p_data[i];
  65. /* Blow away old data and set new data */
  66. fdt_delprop(fdt, offs, "ti,irqs-skip");
  67. ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
  68. temp,
  69. (old_cnt + new_cnt) * sizeof(u32));
  70. free(temp);
  71. /* Check if the update worked */
  72. if (ret < 0) {
  73. printf("Could not add ti,irqs-skip property to node %s: %s\n",
  74. path, fdt_strerror(ret));
  75. return ret;
  76. }
  77. return 0;
  78. }
  79. #if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
  80. (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
  81. static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
  82. {
  83. const char *path;
  84. int offs;
  85. int ret;
  86. u32 temp[2];
  87. /*
  88. * Update SRAM reservations on secure devices. The OCMC RAM
  89. * is always reserved for secure use from the start of that
  90. * memory region
  91. */
  92. path = "/ocp/ocmcram@40300000/sram-hs";
  93. offs = fdt_path_offset(fdt, path);
  94. if (offs < 0) {
  95. debug("Node %s not found.\n", path);
  96. return 0;
  97. }
  98. /* relative start offset */
  99. temp[0] = cpu_to_fdt32(0);
  100. /* reservation size */
  101. temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
  102. CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
  103. fdt_delprop(fdt, offs, "reg");
  104. ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
  105. if (ret < 0) {
  106. printf("Could not add reg property to node %s: %s\n",
  107. path, fdt_strerror(ret));
  108. return ret;
  109. }
  110. return 0;
  111. }
  112. #else
  113. static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd) { return 0; }
  114. #endif
  115. static void ft_hs_fixups(void *fdt, struct bd_info *bd)
  116. {
  117. /* Check we are running on an HS/EMU device type */
  118. if (GP_DEVICE != get_device_type()) {
  119. if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
  120. (ft_hs_disable_rng(fdt, bd) == 0) &&
  121. (ft_hs_fixup_sram(fdt, bd) == 0) &&
  122. (ft_hs_fixup_dram(fdt, bd) == 0) &&
  123. (ft_hs_add_tee(fdt, bd) == 0))
  124. return;
  125. } else {
  126. printf("ERROR: Incorrect device type (GP) detected!");
  127. }
  128. /* Fixup failed or wrong device type */
  129. hang();
  130. }
  131. #else
  132. static void ft_hs_fixups(void *fdt, struct bd_info *bd)
  133. {
  134. }
  135. #endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
  136. #if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
  137. #define OPP_DSP_CLK_NUM 3
  138. #define OPP_IVA_CLK_NUM 2
  139. #define OPP_GPU_CLK_NUM 2
  140. const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
  141. "dpll_dsp_ck",
  142. "dpll_dsp_m2_ck",
  143. "dpll_dsp_m3x2_ck",
  144. };
  145. const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
  146. "dpll_iva_ck",
  147. "dpll_iva_m2_ck",
  148. };
  149. const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
  150. "dpll_gpu_ck",
  151. "dpll_gpu_m2_ck",
  152. };
  153. /* DSPEVE voltage domain */
  154. u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
  155. {}, /*OPP_LOW */
  156. {600000000, 600000000, 400000000}, /* OPP_NOM */
  157. {700000000, 700000000, 466666667}, /* OPP_OD */
  158. {750000000, 750000000, 500000000}, /* OPP_HIGH */
  159. };
  160. /* DSP clock rates on DRA76x ACD-package based SoCs */
  161. u32 dra76_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
  162. {}, /* OPP_LOW */
  163. {600000000, 600000000, 400000000}, /* OPP_NOM */
  164. {700000000, 700000000, 466666667}, /* OPP_OD */
  165. {850000000, 850000000, 566666667}, /* OPP_HIGH */
  166. };
  167. /* IVA voltage domain */
  168. u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
  169. {}, /* OPP_LOW */
  170. {1165000000, 388333334}, /* OPP_NOM */
  171. {860000000, 430000000}, /* OPP_OD */
  172. {1064000000, 532000000}, /* OPP_HIGH */
  173. };
  174. /* GPU voltage domain */
  175. u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
  176. {}, /* OPP_LOW */
  177. {1277000000, 425666667}, /* OPP_NOM */
  178. {1000000000, 500000000}, /* OPP_OD */
  179. {1064000000, 532000000}, /* OPP_HIGH */
  180. };
  181. static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
  182. {
  183. int offs, node_offs, ret, i;
  184. uint32_t phandle;
  185. offs = fdt_path_offset(fdt, "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks");
  186. if (offs < 0)
  187. offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
  188. if (offs < 0) {
  189. debug("Could not find cm_core_aon clocks node path offset : %s\n",
  190. fdt_strerror(offs));
  191. return offs;
  192. }
  193. for (i = 0; i < num; i++) {
  194. node_offs = fdt_subnode_offset(fdt, offs, names[i]);
  195. if (node_offs < 0) {
  196. debug("Could not find clock sub-node %s: %s\n",
  197. names[i], fdt_strerror(node_offs));
  198. return offs;
  199. }
  200. phandle = fdt_get_phandle(fdt, node_offs);
  201. if (!phandle) {
  202. debug("Could not find phandle for clock %s\n",
  203. names[i]);
  204. return -1;
  205. }
  206. ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
  207. phandle);
  208. if (ret < 0) {
  209. debug("Could not add assigned-clocks property to clock node %s: %s\n",
  210. names[i], fdt_strerror(ret));
  211. return ret;
  212. }
  213. ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
  214. rates[i]);
  215. if (ret < 0) {
  216. debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
  217. names[i], fdt_strerror(ret));
  218. return ret;
  219. }
  220. }
  221. return 0;
  222. }
  223. static void ft_opp_clock_fixups(void *fdt, struct bd_info *bd)
  224. {
  225. const char **clk_names;
  226. u32 *clk_rates;
  227. int ret;
  228. if (!is_dra72x() && !is_dra7xx())
  229. return;
  230. /* fixup DSP clocks */
  231. clk_names = dra7_opp_dsp_clk_names;
  232. clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
  233. /* adjust for higher OPP_HIGH clock rate on DRA76xP/DRA77xP SoCs */
  234. if (is_dra76x_acd())
  235. clk_rates = dra76_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
  236. ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
  237. if (ret) {
  238. printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
  239. fdt_strerror(ret));
  240. return;
  241. }
  242. /* fixup IVA clocks */
  243. clk_names = dra7_opp_iva_clk_names;
  244. clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
  245. ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
  246. if (ret) {
  247. printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
  248. fdt_strerror(ret));
  249. return;
  250. }
  251. /* fixup GPU clocks */
  252. clk_names = dra7_opp_gpu_clk_names;
  253. clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
  254. ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
  255. if (ret) {
  256. printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
  257. fdt_strerror(ret));
  258. return;
  259. }
  260. }
  261. #else
  262. static void ft_opp_clock_fixups(void *fdt, struct bd_info *bd) { }
  263. #endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
  264. /*
  265. * Place for general cpu/SoC FDT fixups. Board specific
  266. * fixups should remain in the board files which is where
  267. * this function should be called from.
  268. */
  269. void ft_cpu_setup(void *fdt, struct bd_info *bd)
  270. {
  271. ft_hs_fixups(fdt, bd);
  272. ft_opp_clock_fixups(fdt, bd);
  273. }