spl_id_nand.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Tom Rini <trini@ti.com>
  8. *
  9. * Initial Code from:
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Jian Zhang <jzhang@ti.com>
  12. */
  13. #include <common.h>
  14. #include <jffs2/load_kernel.h>
  15. #include <linux/mtd/rawnand.h>
  16. #include <linux/mtd/omap_gpmc.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/mem.h>
  20. /*
  21. * Many boards will want to know the results of the NAND_CMD_READID command
  22. * in order to decide what to do about DDR initialization. This function
  23. * allows us to do that very early and to pass those results back to the
  24. * board so it can make whatever decisions need to be made.
  25. */
  26. int identify_nand_chip(int *mfr, int *id)
  27. {
  28. int loops = 1000;
  29. /* Make sure that we have setup GPMC for NAND correctly. */
  30. set_gpmc_cs0(MTD_DEV_TYPE_NAND);
  31. sdelay(2000);
  32. /* Issue a RESET and then READID */
  33. writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  34. writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  35. while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  36. != NAND_STATUS_READY) {
  37. sdelay(100);
  38. if (--loops == 0)
  39. return 1;
  40. }
  41. writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
  42. /* Set the address to read to 0x0 */
  43. writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
  44. /* Read off the manufacturer and device id. */
  45. *mfr = readb(&gpmc_cfg->cs[0].nand_dat);
  46. *id = readb(&gpmc_cfg->cs[0].nand_dat);
  47. return 0;
  48. }