emif4.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * emif4.c
  4. *
  5. * AM33XX emif4 configuration file
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/ddr_defs.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/io.h>
  16. #include <asm/emif.h>
  17. static struct vtp_reg *vtpreg[2] = {
  18. (struct vtp_reg *)VTP0_CTRL_ADDR,
  19. (struct vtp_reg *)VTP1_CTRL_ADDR};
  20. #ifdef CONFIG_AM33XX
  21. static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  22. #endif
  23. #ifdef CONFIG_AM43XX
  24. static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  25. static struct cm_device_inst *cm_device =
  26. (struct cm_device_inst *)CM_DEVICE_INST;
  27. #endif
  28. #ifdef CONFIG_TI814X
  29. void config_dmm(const struct dmm_lisa_map_regs *regs)
  30. {
  31. struct dmm_lisa_map_regs *hw_lisa_map_regs =
  32. (struct dmm_lisa_map_regs *)DMM_BASE;
  33. enable_dmm_clocks();
  34. writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  35. writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  36. writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  37. writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  38. writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  39. writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  40. writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  41. writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  42. }
  43. #endif
  44. static void config_vtp(int nr)
  45. {
  46. writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  47. &vtpreg[nr]->vtp0ctrlreg);
  48. writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  49. &vtpreg[nr]->vtp0ctrlreg);
  50. writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  51. &vtpreg[nr]->vtp0ctrlreg);
  52. /* Poll for READY */
  53. while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  54. VTP_CTRL_READY)
  55. ;
  56. }
  57. void __weak ddr_pll_config(unsigned int ddrpll_m)
  58. {
  59. }
  60. void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
  61. const struct ddr_data *data, const struct cmd_control *ctrl,
  62. const struct emif_regs *regs, int nr)
  63. {
  64. ddr_pll_config(pll);
  65. config_vtp(nr);
  66. config_cmd_ctrl(ctrl, nr);
  67. config_ddr_data(data, nr);
  68. #ifdef CONFIG_AM33XX
  69. config_io_ctrl(ioregs);
  70. /* Set CKE to be controlled by EMIF/DDR PHY */
  71. writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
  72. #endif
  73. #ifdef CONFIG_AM43XX
  74. writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
  75. while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
  76. ;
  77. config_io_ctrl(ioregs);
  78. /* Set CKE to be controlled by EMIF/DDR PHY */
  79. writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
  80. if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
  81. #ifndef CONFIG_SPL_RTC_DDR_SUPPORT
  82. /* Allow EMIF to control DDR_RESET */
  83. writel(0x00000000, &ddrctrl->ddrioctrl);
  84. #else
  85. /* Override EMIF DDR_RESET control */
  86. writel(0x80000000, &ddrctrl->ddrioctrl);
  87. #endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
  88. #endif
  89. /* Program EMIF instance */
  90. config_ddr_phy(regs, nr);
  91. set_sdram_timings(regs, nr);
  92. if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
  93. config_sdram_emif4d5(regs, nr);
  94. else
  95. config_sdram(regs, nr);
  96. }