ddr.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DDR Configuration for AM33xx devices.
  4. *
  5. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/ddr_defs.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. #include <asm/emif.h>
  14. #include <linux/delay.h>
  15. /**
  16. * Base address for EMIF instances
  17. */
  18. static struct emif_reg_struct *emif_reg[2] = {
  19. (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  20. (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  21. /**
  22. * Base addresses for DDR PHY cmd/data regs
  23. */
  24. static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  25. (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  26. (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  27. static struct ddr_data_regs *ddr_data_reg[2] = {
  28. (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  29. (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  30. /**
  31. * Base address for ddr io control instances
  32. */
  33. static struct ddr_cmdtctrl *ioctrl_reg = {
  34. (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  35. static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  36. {
  37. u32 mr;
  38. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  39. writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  40. mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  41. debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  42. if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
  43. ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  44. ((mr & 0xff000000) >> 24) == (mr & 0xff))
  45. return mr & 0xff;
  46. else
  47. return mr;
  48. }
  49. static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  50. {
  51. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  52. writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  53. writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  54. }
  55. static void configure_mr(int nr, u32 cs)
  56. {
  57. u32 mr_addr;
  58. while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  59. ;
  60. set_mr(nr, cs, LPDDR2_MR10, 0x56);
  61. set_mr(nr, cs, LPDDR2_MR1, 0x43);
  62. set_mr(nr, cs, LPDDR2_MR2, 0x2);
  63. mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  64. set_mr(nr, cs, mr_addr, 0x2);
  65. }
  66. /*
  67. * Configure EMIF4D5 registers and MR registers For details about these magic
  68. * values please see the EMIF registers section of the TRM.
  69. */
  70. void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  71. {
  72. #ifdef CONFIG_AM43XX
  73. struct prm_device_inst *prm_device =
  74. (struct prm_device_inst *)PRM_DEVICE_INST;
  75. #endif
  76. writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  77. writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  78. writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  79. writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  80. writel(regs->emif_rd_wr_lvl_rmp_win,
  81. &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  82. writel(regs->emif_rd_wr_lvl_rmp_ctl,
  83. &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  84. writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  85. writel(regs->emif_rd_wr_exec_thresh,
  86. &emif_reg[nr]->emif_rd_wr_exec_thresh);
  87. /*
  88. * for most SOCs these registers won't need to be changed so only
  89. * write to these registers if someone explicitly has set the
  90. * register's value.
  91. */
  92. if(regs->emif_cos_config) {
  93. writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
  94. writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
  95. writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
  96. writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
  97. }
  98. /*
  99. * Sequence to ensure that the PHY is in a known state prior to
  100. * startting hardware leveling. Also acts as to latch some state from
  101. * the EMIF into the PHY.
  102. */
  103. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  104. writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
  105. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  106. clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
  107. EMIF_REG_INITREF_DIS_MASK);
  108. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  109. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  110. /* Wait 1ms because of L3 timeout error */
  111. udelay(1000);
  112. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  113. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  114. #ifdef CONFIG_AM43XX
  115. /*
  116. * Disable EMIF_DEVOFF
  117. * -> Cold Boot: This is just rewriting the default register value.
  118. * -> RTC Resume: Must disable DEVOFF before leveling.
  119. */
  120. writel(0, &prm_device->emif_ctrl);
  121. #endif
  122. /* Perform hardware leveling for DDR3 */
  123. if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
  124. writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
  125. 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
  126. writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
  127. 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
  128. writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  129. /* Enable read leveling */
  130. writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  131. /* Wait 1ms because of L3 timeout error */
  132. udelay(1000);
  133. /*
  134. * Enable full read and write leveling. Wait for read and write
  135. * leveling bit to clear RDWRLVLFULL_START bit 31
  136. */
  137. while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
  138. != 0)
  139. ;
  140. /* Check the timeout register to see if leveling is complete */
  141. if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
  142. puts("DDR3 H/W leveling incomplete with errors\n");
  143. } else {
  144. /* DDR2 */
  145. configure_mr(nr, 0);
  146. configure_mr(nr, 1);
  147. }
  148. }
  149. /**
  150. * Configure SDRAM
  151. */
  152. void config_sdram(const struct emif_regs *regs, int nr)
  153. {
  154. #ifdef CONFIG_TI816X
  155. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  156. writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
  157. writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
  158. writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */
  159. writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */
  160. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  161. #else
  162. if (regs->zq_config) {
  163. writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  164. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  165. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  166. /* Trigger initialization */
  167. writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
  168. /* Wait 1ms because of L3 timeout error */
  169. udelay(1000);
  170. /* Write proper sdram_ref_cref_ctrl value */
  171. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  172. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  173. }
  174. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  175. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  176. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  177. /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
  178. if (regs->ocp_config)
  179. writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
  180. #endif
  181. }
  182. /**
  183. * Set SDRAM timings
  184. */
  185. void set_sdram_timings(const struct emif_regs *regs, int nr)
  186. {
  187. writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
  188. writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
  189. writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
  190. writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
  191. writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
  192. writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
  193. }
  194. /*
  195. * Configure EXT PHY registers for software leveling
  196. */
  197. static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
  198. {
  199. u32 *ext_phy_ctrl_base = 0;
  200. u32 *emif_ext_phy_ctrl_base = 0;
  201. __maybe_unused const u32 *ext_phy_ctrl_const_regs;
  202. u32 i = 0;
  203. __maybe_unused u32 size;
  204. ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
  205. emif_ext_phy_ctrl_base =
  206. (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  207. /* Configure external phy control timing registers */
  208. for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
  209. writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
  210. /* Update shadow registers */
  211. writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
  212. }
  213. #ifdef CONFIG_AM43XX
  214. /*
  215. * External phy 6-24 registers do not change with ddr frequency.
  216. * These only need to be set on DDR2 on AM43xx.
  217. */
  218. emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
  219. if (!size)
  220. return;
  221. for (i = 0; i < size; i++) {
  222. writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
  223. /* Update shadow registers */
  224. writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
  225. }
  226. #endif
  227. }
  228. /*
  229. * Configure EXT PHY registers for hardware leveling
  230. */
  231. static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
  232. {
  233. /*
  234. * Enable hardware leveling on the EMIF. For details about these
  235. * magic values please see the EMIF registers section of the TRM.
  236. */
  237. if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
  238. /* PHY_INVERT_CLKOUT = 1 */
  239. writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  240. writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
  241. } else {
  242. /* PHY_INVERT_CLKOUT = 0 */
  243. writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  244. writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
  245. }
  246. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
  247. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
  248. writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
  249. writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
  250. writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
  251. writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
  252. writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
  253. writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
  254. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
  255. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
  256. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
  257. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
  258. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
  259. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
  260. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
  261. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
  262. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
  263. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
  264. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
  265. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
  266. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
  267. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
  268. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
  269. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
  270. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
  271. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
  272. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
  273. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
  274. writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
  275. writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
  276. /*
  277. * Sequence to ensure that the PHY is again in a known state after
  278. * hardware leveling.
  279. */
  280. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  281. writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
  282. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  283. }
  284. /**
  285. * Configure DDR PHY
  286. */
  287. void config_ddr_phy(const struct emif_regs *regs, int nr)
  288. {
  289. /*
  290. * Disable initialization and refreshes for now until we finish
  291. * programming EMIF regs and set time between rising edge of
  292. * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
  293. * We currently hardcode a value based on a max expected frequency
  294. * of 400MHz.
  295. */
  296. writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
  297. &emif_reg[nr]->emif_sdram_ref_ctrl);
  298. writel(regs->emif_ddr_phy_ctlr_1,
  299. &emif_reg[nr]->emif_ddr_phy_ctrl_1);
  300. writel(regs->emif_ddr_phy_ctlr_1,
  301. &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
  302. if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
  303. if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
  304. ext_phy_settings_hwlvl(regs, nr);
  305. else
  306. ext_phy_settings_swlvl(regs, nr);
  307. }
  308. }
  309. /**
  310. * Configure DDR CMD control registers
  311. */
  312. void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
  313. {
  314. if (!cmd)
  315. return;
  316. writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
  317. writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
  318. writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
  319. writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
  320. writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
  321. writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
  322. }
  323. /**
  324. * Configure DDR DATA registers
  325. */
  326. void config_ddr_data(const struct ddr_data *data, int nr)
  327. {
  328. int i;
  329. if (!data)
  330. return;
  331. for (i = 0; i < DDR_DATA_REGS_NR; i++) {
  332. writel(data->datardsratio0,
  333. &(ddr_data_reg[nr]+i)->dt0rdsratio0);
  334. writel(data->datawdsratio0,
  335. &(ddr_data_reg[nr]+i)->dt0wdsratio0);
  336. writel(data->datawiratio0,
  337. &(ddr_data_reg[nr]+i)->dt0wiratio0);
  338. writel(data->datagiratio0,
  339. &(ddr_data_reg[nr]+i)->dt0giratio0);
  340. writel(data->datafwsratio0,
  341. &(ddr_data_reg[nr]+i)->dt0fwsratio0);
  342. writel(data->datawrsratio0,
  343. &(ddr_data_reg[nr]+i)->dt0wrsratio0);
  344. }
  345. }
  346. void config_io_ctrl(const struct ctrl_ioregs *ioregs)
  347. {
  348. if (!ioregs)
  349. return;
  350. writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
  351. writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
  352. writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
  353. writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
  354. writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
  355. #ifdef CONFIG_AM43XX
  356. writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
  357. writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
  358. writel(ioregs->emif_sdram_config_ext,
  359. &ioctrl_reg->emif_sdram_config_ext);
  360. #endif
  361. }