clock_am43xx.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * clock_am43xx.c
  4. *
  5. * clocks for AM43XX based boards
  6. * Derived from AM33XX based boards
  7. *
  8. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  9. */
  10. #include <common.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/io.h>
  16. struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  17. struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  18. struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  19. const struct dpll_regs dpll_mpu_regs = {
  20. .cm_clkmode_dpll = CM_WKUP + 0x560,
  21. .cm_idlest_dpll = CM_WKUP + 0x564,
  22. .cm_clksel_dpll = CM_WKUP + 0x56c,
  23. .cm_div_m2_dpll = CM_WKUP + 0x570,
  24. };
  25. const struct dpll_regs dpll_core_regs = {
  26. .cm_clkmode_dpll = CM_WKUP + 0x520,
  27. .cm_idlest_dpll = CM_WKUP + 0x524,
  28. .cm_clksel_dpll = CM_WKUP + 0x52C,
  29. .cm_div_m4_dpll = CM_WKUP + 0x538,
  30. .cm_div_m5_dpll = CM_WKUP + 0x53C,
  31. .cm_div_m6_dpll = CM_WKUP + 0x540,
  32. };
  33. const struct dpll_regs dpll_per_regs = {
  34. .cm_clkmode_dpll = CM_WKUP + 0x5E0,
  35. .cm_idlest_dpll = CM_WKUP + 0x5E4,
  36. .cm_clksel_dpll = CM_WKUP + 0x5EC,
  37. .cm_div_m2_dpll = CM_WKUP + 0x5F0,
  38. };
  39. const struct dpll_regs dpll_ddr_regs = {
  40. .cm_clkmode_dpll = CM_WKUP + 0x5A0,
  41. .cm_idlest_dpll = CM_WKUP + 0x5A4,
  42. .cm_clksel_dpll = CM_WKUP + 0x5AC,
  43. .cm_div_m2_dpll = CM_WKUP + 0x5B0,
  44. .cm_div_m4_dpll = CM_WKUP + 0x5B8,
  45. };
  46. void setup_clocks_for_console(void)
  47. {
  48. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
  49. /* Do not add any spl_debug prints in this function */
  50. clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  51. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  52. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  53. /* Enable UART0 */
  54. clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
  55. MODULE_CLKCTRL_MODULEMODE_MASK,
  56. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  57. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  58. while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
  59. (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
  60. clkctrl = readl(&cmwkup->wkup_uart0ctrl);
  61. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  62. MODULE_CLKCTRL_IDLEST_SHIFT;
  63. }
  64. }
  65. void enable_basic_clocks(void)
  66. {
  67. u32 *const clk_domains[] = {
  68. &cmper->l3clkstctrl,
  69. &cmper->l3sclkstctrl,
  70. &cmper->l4lsclkstctrl,
  71. &cmwkup->wkclkstctrl,
  72. &cmper->emifclkstctrl,
  73. 0
  74. };
  75. u32 *const clk_modules_explicit_en[] = {
  76. &cmper->l3clkctrl,
  77. &cmper->l4lsclkctrl,
  78. &cmper->l4fwclkctrl,
  79. &cmwkup->wkl4wkclkctrl,
  80. &cmper->l3instrclkctrl,
  81. &cmper->l4hsclkctrl,
  82. &cmwkup->wkgpio0clkctrl,
  83. &cmwkup->wkctrlclkctrl,
  84. &cmper->timer2clkctrl,
  85. &cmper->gpmcclkctrl,
  86. &cmper->elmclkctrl,
  87. &cmper->mmc0clkctrl,
  88. &cmper->mmc1clkctrl,
  89. &cmwkup->wkup_i2c0ctrl,
  90. &cmper->gpio1clkctrl,
  91. &cmper->gpio2clkctrl,
  92. &cmper->gpio3clkctrl,
  93. &cmper->gpio4clkctrl,
  94. &cmper->gpio5clkctrl,
  95. &cmper->i2c1clkctrl,
  96. &cmper->cpgmac0clkctrl,
  97. &cmper->emiffwclkctrl,
  98. &cmper->emifclkctrl,
  99. &cmper->otfaemifclkctrl,
  100. &cmper->qspiclkctrl,
  101. &cmper->spi0clkctrl,
  102. 0
  103. };
  104. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  105. /* Select the Master osc clk as Timer2 clock source */
  106. writel(0x1, &cmdpll->clktimer2clk);
  107. /* For OPP100 the mac clock should be /5. */
  108. writel(0x4, &cmdpll->clkselmacclk);
  109. }
  110. void rtc_only_enable_basic_clocks(void)
  111. {
  112. u32 *const clk_domains[] = {
  113. &cmper->emifclkstctrl,
  114. 0
  115. };
  116. u32 *const clk_modules_explicit_en[] = {
  117. &cmper->gpio5clkctrl,
  118. &cmper->emiffwclkctrl,
  119. &cmper->emifclkctrl,
  120. &cmper->otfaemifclkctrl,
  121. 0
  122. };
  123. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  124. /* Select the Master osc clk as Timer2 clock source */
  125. writel(0x1, &cmdpll->clktimer2clk);
  126. }
  127. #ifdef CONFIG_TI_EDMA3
  128. void enable_edma3_clocks(void)
  129. {
  130. u32 *const clk_domains_edma3[] = {
  131. 0
  132. };
  133. u32 *const clk_modules_explicit_en_edma3[] = {
  134. &cmper->tpccclkctrl,
  135. &cmper->tptc0clkctrl,
  136. 0
  137. };
  138. do_enable_clocks(clk_domains_edma3,
  139. clk_modules_explicit_en_edma3,
  140. 1);
  141. }
  142. void disable_edma3_clocks(void)
  143. {
  144. u32 *const clk_domains_edma3[] = {
  145. 0
  146. };
  147. u32 *const clk_modules_disable_edma3[] = {
  148. &cmper->tpccclkctrl,
  149. &cmper->tptc0clkctrl,
  150. 0
  151. };
  152. do_disable_clocks(clk_domains_edma3,
  153. clk_modules_disable_edma3,
  154. 1);
  155. }
  156. #endif
  157. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  158. void enable_usb_clocks(int index)
  159. {
  160. u32 *usbclkctrl = 0;
  161. u32 *usbphyocp2scpclkctrl = 0;
  162. if (index == 0) {
  163. usbclkctrl = &cmper->usb0clkctrl;
  164. usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
  165. setbits_le32(&cmper->usb0clkctrl,
  166. USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
  167. setbits_le32(&cmwkup->usbphy0clkctrl,
  168. USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
  169. } else if (index == 1) {
  170. usbclkctrl = &cmper->usb1clkctrl;
  171. usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
  172. setbits_le32(&cmper->usb1clkctrl,
  173. USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
  174. setbits_le32(&cmwkup->usbphy1clkctrl,
  175. USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
  176. }
  177. u32 *const clk_domains_usb[] = {
  178. 0
  179. };
  180. u32 *const clk_modules_explicit_en_usb[] = {
  181. usbclkctrl,
  182. usbphyocp2scpclkctrl,
  183. 0
  184. };
  185. do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
  186. }
  187. void disable_usb_clocks(int index)
  188. {
  189. u32 *usbclkctrl = 0;
  190. u32 *usbphyocp2scpclkctrl = 0;
  191. if (index == 0) {
  192. usbclkctrl = &cmper->usb0clkctrl;
  193. usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
  194. clrbits_le32(&cmper->usb0clkctrl,
  195. USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
  196. clrbits_le32(&cmwkup->usbphy0clkctrl,
  197. USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
  198. } else if (index == 1) {
  199. usbclkctrl = &cmper->usb1clkctrl;
  200. usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
  201. clrbits_le32(&cmper->usb1clkctrl,
  202. USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
  203. clrbits_le32(&cmwkup->usbphy1clkctrl,
  204. USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
  205. }
  206. u32 *const clk_domains_usb[] = {
  207. 0
  208. };
  209. u32 *const clk_modules_disable_usb[] = {
  210. usbclkctrl,
  211. usbphyocp2scpclkctrl,
  212. 0
  213. };
  214. do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
  215. }
  216. #endif