board.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Common board functions for AM33XX based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <debug_uart.h>
  12. #include <errno.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <ns16550.h>
  16. #include <spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/i2c.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/io.h>
  28. #include <asm/emif.h>
  29. #include <asm/gpio.h>
  30. #include <asm/omap_common.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <linux/delay.h>
  35. #include <linux/errno.h>
  36. #include <linux/compiler.h>
  37. #include <linux/usb/ch9.h>
  38. #include <linux/usb/gadget.h>
  39. #include <linux/usb/musb.h>
  40. #include <asm/omap_musb.h>
  41. #include <asm/davinci_rtc.h>
  42. #define AM43XX_EMIF_BASE 0x4C000000
  43. #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
  44. #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
  45. #define AM43XX_SDRAM_TYPE_SHIFT 29
  46. #define AM43XX_SDRAM_TYPE_DDR3 3
  47. #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
  48. #define AM43XX_RDWRLVLFULL_START 0x80000000
  49. DECLARE_GLOBAL_DATA_PTR;
  50. int dram_init(void)
  51. {
  52. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  53. sdram_init();
  54. #endif
  55. /* dram_init must store complete ramsize in gd->ram_size */
  56. gd->ram_size = get_ram_size(
  57. (void *)CONFIG_SYS_SDRAM_BASE,
  58. CONFIG_MAX_RAM_BANK_SIZE);
  59. return 0;
  60. }
  61. int dram_init_banksize(void)
  62. {
  63. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  64. gd->bd->bi_dram[0].size = gd->ram_size;
  65. return 0;
  66. }
  67. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  68. static const struct ns16550_platdata am33xx_serial[] = {
  69. { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  70. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  71. # ifdef CONFIG_SYS_NS16550_COM2
  72. { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  73. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  74. # ifdef CONFIG_SYS_NS16550_COM3
  75. { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  76. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  77. { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  78. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  79. { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  80. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  81. { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  82. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  83. # endif
  84. # endif
  85. };
  86. U_BOOT_DEVICES(am33xx_uarts) = {
  87. { "ns16550_serial", &am33xx_serial[0] },
  88. # ifdef CONFIG_SYS_NS16550_COM2
  89. { "ns16550_serial", &am33xx_serial[1] },
  90. # ifdef CONFIG_SYS_NS16550_COM3
  91. { "ns16550_serial", &am33xx_serial[2] },
  92. { "ns16550_serial", &am33xx_serial[3] },
  93. { "ns16550_serial", &am33xx_serial[4] },
  94. { "ns16550_serial", &am33xx_serial[5] },
  95. # endif
  96. # endif
  97. };
  98. #ifdef CONFIG_DM_I2C
  99. static const struct omap_i2c_platdata am33xx_i2c[] = {
  100. { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
  101. { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
  102. { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
  103. };
  104. U_BOOT_DEVICES(am33xx_i2c) = {
  105. { "i2c_omap", &am33xx_i2c[0] },
  106. { "i2c_omap", &am33xx_i2c[1] },
  107. { "i2c_omap", &am33xx_i2c[2] },
  108. };
  109. #endif
  110. #if CONFIG_IS_ENABLED(DM_GPIO)
  111. static const struct omap_gpio_platdata am33xx_gpio[] = {
  112. { 0, AM33XX_GPIO0_BASE },
  113. { 1, AM33XX_GPIO1_BASE },
  114. { 2, AM33XX_GPIO2_BASE },
  115. { 3, AM33XX_GPIO3_BASE },
  116. #ifdef CONFIG_AM43XX
  117. { 4, AM33XX_GPIO4_BASE },
  118. { 5, AM33XX_GPIO5_BASE },
  119. #endif
  120. };
  121. U_BOOT_DEVICES(am33xx_gpios) = {
  122. { "gpio_omap", &am33xx_gpio[0] },
  123. { "gpio_omap", &am33xx_gpio[1] },
  124. { "gpio_omap", &am33xx_gpio[2] },
  125. { "gpio_omap", &am33xx_gpio[3] },
  126. #ifdef CONFIG_AM43XX
  127. { "gpio_omap", &am33xx_gpio[4] },
  128. { "gpio_omap", &am33xx_gpio[5] },
  129. #endif
  130. };
  131. #endif
  132. #endif
  133. #if !CONFIG_IS_ENABLED(DM_GPIO)
  134. static const struct gpio_bank gpio_bank_am33xx[] = {
  135. { (void *)AM33XX_GPIO0_BASE },
  136. { (void *)AM33XX_GPIO1_BASE },
  137. { (void *)AM33XX_GPIO2_BASE },
  138. { (void *)AM33XX_GPIO3_BASE },
  139. #ifdef CONFIG_AM43XX
  140. { (void *)AM33XX_GPIO4_BASE },
  141. { (void *)AM33XX_GPIO5_BASE },
  142. #endif
  143. };
  144. const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  145. #endif
  146. #if defined(CONFIG_MMC_OMAP_HS)
  147. int cpu_mmc_init(struct bd_info *bis)
  148. {
  149. int ret;
  150. ret = omap_mmc_init(0, 0, 0, -1, -1);
  151. if (ret)
  152. return ret;
  153. return omap_mmc_init(1, 0, 0, -1, -1);
  154. }
  155. #endif
  156. /*
  157. * RTC only with DDR in self-refresh mode magic value, checked against during
  158. * boot to see if we have a valid config. This should be in sync with the value
  159. * that will be in drivers/soc/ti/pm33xx.c.
  160. */
  161. #define RTC_MAGIC_VAL 0x8cd0
  162. /* Board type field bit shift for RTC only with DDR in self-refresh mode */
  163. #define RTC_BOARD_TYPE_SHIFT 16
  164. /* AM33XX has two MUSB controllers which can be host or gadget */
  165. #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
  166. (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
  167. (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
  168. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
  169. static struct musb_hdrc_config musb_config = {
  170. .multipoint = 1,
  171. .dyn_fifo = 1,
  172. .num_eps = 16,
  173. .ram_bits = 12,
  174. };
  175. #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
  176. static struct ti_musb_platdata usb0 = {
  177. .base = (void *)USB0_OTG_BASE,
  178. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
  179. .plat = {
  180. .config = &musb_config,
  181. .power = 50,
  182. .platform_ops = &musb_dsps_ops,
  183. },
  184. };
  185. static struct ti_musb_platdata usb1 = {
  186. .base = (void *)USB1_OTG_BASE,
  187. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
  188. .plat = {
  189. .config = &musb_config,
  190. .power = 50,
  191. .platform_ops = &musb_dsps_ops,
  192. },
  193. };
  194. U_BOOT_DEVICES(am33xx_usbs) = {
  195. #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
  196. { "ti-musb-peripheral", &usb0 },
  197. #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
  198. { "ti-musb-host", &usb0 },
  199. #endif
  200. #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
  201. { "ti-musb-peripheral", &usb1 },
  202. #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
  203. { "ti-musb-host", &usb1 },
  204. #endif
  205. };
  206. int arch_misc_init(void)
  207. {
  208. return 0;
  209. }
  210. #else
  211. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  212. /* USB 2.0 PHY Control */
  213. #define CM_PHY_PWRDN (1 << 0)
  214. #define CM_PHY_OTG_PWRDN (1 << 1)
  215. #define OTGVDET_EN (1 << 19)
  216. #define OTGSESSENDEN (1 << 20)
  217. static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
  218. {
  219. if (on) {
  220. clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
  221. OTGVDET_EN | OTGSESSENDEN);
  222. } else {
  223. clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
  224. }
  225. }
  226. #ifdef CONFIG_AM335X_USB0
  227. static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
  228. {
  229. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
  230. }
  231. struct omap_musb_board_data otg0_board_data = {
  232. .set_phy_power = am33xx_otg0_set_phy_power,
  233. };
  234. static struct musb_hdrc_platform_data otg0_plat = {
  235. .mode = CONFIG_AM335X_USB0_MODE,
  236. .config = &musb_config,
  237. .power = 50,
  238. .platform_ops = &musb_dsps_ops,
  239. .board_data = &otg0_board_data,
  240. };
  241. #endif
  242. #ifdef CONFIG_AM335X_USB1
  243. static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
  244. {
  245. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
  246. }
  247. struct omap_musb_board_data otg1_board_data = {
  248. .set_phy_power = am33xx_otg1_set_phy_power,
  249. };
  250. static struct musb_hdrc_platform_data otg1_plat = {
  251. .mode = CONFIG_AM335X_USB1_MODE,
  252. .config = &musb_config,
  253. .power = 50,
  254. .platform_ops = &musb_dsps_ops,
  255. .board_data = &otg1_board_data,
  256. };
  257. #endif
  258. int arch_misc_init(void)
  259. {
  260. #ifdef CONFIG_AM335X_USB0
  261. musb_register(&otg0_plat, &otg0_board_data,
  262. (void *)USB0_OTG_BASE);
  263. #endif
  264. #ifdef CONFIG_AM335X_USB1
  265. musb_register(&otg1_plat, &otg1_board_data,
  266. (void *)USB1_OTG_BASE);
  267. #endif
  268. return 0;
  269. }
  270. #endif
  271. #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  272. int arch_misc_init(void)
  273. {
  274. struct udevice *dev;
  275. int ret;
  276. ret = uclass_first_device(UCLASS_MISC, &dev);
  277. if (ret || !dev)
  278. return ret;
  279. #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
  280. ret = usb_ether_init();
  281. if (ret) {
  282. pr_err("USB ether init failed\n");
  283. return ret;
  284. }
  285. #endif
  286. return 0;
  287. }
  288. #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  289. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  290. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
  291. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
  292. static void rtc32k_unlock(struct davinci_rtc *rtc)
  293. {
  294. /*
  295. * Unlock the RTC's registers. For more details please see the
  296. * RTC_SS section of the TRM. In order to unlock we need to
  297. * write these specific values (keys) in this order.
  298. */
  299. writel(RTC_KICK0R_WE, &rtc->kick0r);
  300. writel(RTC_KICK1R_WE, &rtc->kick1r);
  301. }
  302. #endif
  303. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  304. /*
  305. * Write contents of the RTC_SCRATCH1 register based on board type
  306. * Two things are passed
  307. * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
  308. * control gets to kernel, kernel reads the scratchpad register and gets to
  309. * know that bootloader has rtc_only support.
  310. *
  311. * Second important thing is the board type (16:31). This is needed in the
  312. * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
  313. * identify the board type and we go ahead and copy the board strings to
  314. * am43xx_board_name.
  315. */
  316. void update_rtc_magic(void)
  317. {
  318. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  319. u32 magic = RTC_MAGIC_VAL;
  320. magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
  321. rtc32k_unlock(rtc);
  322. /* write magic */
  323. writel(magic, &rtc->scratch1);
  324. }
  325. #endif
  326. /*
  327. * In the case of non-SPL based booting we'll want to call these
  328. * functions a tiny bit later as it will require gd to be set and cleared
  329. * and that's not true in s_init in this case so we cannot do it there.
  330. */
  331. int board_early_init_f(void)
  332. {
  333. set_mux_conf_regs();
  334. prcm_init();
  335. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  336. update_rtc_magic();
  337. #endif
  338. return 0;
  339. }
  340. /*
  341. * This function is the place to do per-board things such as ramp up the
  342. * MPU clock frequency.
  343. */
  344. __weak void am33xx_spl_board_init(void)
  345. {
  346. }
  347. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  348. static void rtc32k_enable(void)
  349. {
  350. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  351. rtc32k_unlock(rtc);
  352. /* Enable the RTC 32K OSC by setting bits 3 and 6. */
  353. writel((1 << 3) | (1 << 6), &rtc->osc);
  354. }
  355. #endif
  356. static void uart_soft_reset(void)
  357. {
  358. struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  359. u32 regval;
  360. regval = readl(&uart_base->uartsyscfg);
  361. regval |= UART_RESET;
  362. writel(regval, &uart_base->uartsyscfg);
  363. while ((readl(&uart_base->uartsyssts) &
  364. UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  365. ;
  366. /* Disable smart idle */
  367. regval = readl(&uart_base->uartsyscfg);
  368. regval |= UART_SMART_IDLE_EN;
  369. writel(regval, &uart_base->uartsyscfg);
  370. }
  371. static void watchdog_disable(void)
  372. {
  373. struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  374. writel(0xAAAA, &wdtimer->wdtwspr);
  375. while (readl(&wdtimer->wdtwwps) != 0x0)
  376. ;
  377. writel(0x5555, &wdtimer->wdtwspr);
  378. while (readl(&wdtimer->wdtwwps) != 0x0)
  379. ;
  380. }
  381. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  382. /*
  383. * Check if we are executing rtc-only + DDR mode, and resume from it if needed
  384. */
  385. static void rtc_only(void)
  386. {
  387. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  388. struct prm_device_inst *prm_device =
  389. (struct prm_device_inst *)PRM_DEVICE_INST;
  390. u32 scratch1, sdrc;
  391. void (*resume_func)(void);
  392. scratch1 = readl(&rtc->scratch1);
  393. /*
  394. * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
  395. * written to this register when we want to wake up from RTC only
  396. * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
  397. * bits 0-15: RTC_MAGIC_VAL
  398. * bits 16-31: board type (needed for sdram_init)
  399. */
  400. if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
  401. return;
  402. rtc32k_unlock(rtc);
  403. /* Clear RTC magic */
  404. writel(0, &rtc->scratch1);
  405. /*
  406. * Update board type based on value stored on RTC_SCRATCH1, this
  407. * is done so that we don't need to read the board type from eeprom
  408. * over i2c bus which is expensive
  409. */
  410. rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
  411. /*
  412. * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
  413. * are resuming from self-refresh. This avoids an unnecessary re-init
  414. * of the DDR. The re-init takes time and we would need to wait for
  415. * it to complete before accessing DDR to avoid L3 NOC errors.
  416. */
  417. writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
  418. rtc_only_prcm_init();
  419. sdram_init();
  420. /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
  421. /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
  422. sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
  423. sdrc &= AM43XX_SDRAM_TYPE_MASK;
  424. sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
  425. if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
  426. writel(AM43XX_RDWRLVLFULL_START,
  427. AM43XX_EMIF_BASE +
  428. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  429. mdelay(1);
  430. am43xx_wait:
  431. sdrc = readl(AM43XX_EMIF_BASE +
  432. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  433. if (sdrc == AM43XX_RDWRLVLFULL_START)
  434. goto am43xx_wait;
  435. }
  436. resume_func = (void *)readl(&rtc->scratch0);
  437. if (resume_func)
  438. resume_func();
  439. }
  440. #endif
  441. void s_init(void)
  442. {
  443. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  444. rtc_only();
  445. #endif
  446. }
  447. void early_system_init(void)
  448. {
  449. /*
  450. * The ROM will only have set up sufficient pinmux to allow for the
  451. * first 4KiB NOR to be read, we must finish doing what we know of
  452. * the NOR mux in this space in order to continue.
  453. */
  454. #ifdef CONFIG_NOR_BOOT
  455. enable_norboot_pin_mux();
  456. #endif
  457. watchdog_disable();
  458. set_uart_mux_conf();
  459. setup_early_clocks();
  460. uart_soft_reset();
  461. #ifdef CONFIG_SPL_BUILD
  462. /*
  463. * Save the boot parameters passed from romcode.
  464. * We cannot delay the saving further than this,
  465. * to prevent overwrites.
  466. */
  467. save_omap_boot_params();
  468. #endif
  469. #ifdef CONFIG_DEBUG_UART_OMAP
  470. debug_uart_init();
  471. #endif
  472. #ifdef CONFIG_SPL_BUILD
  473. spl_early_init();
  474. #endif
  475. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  476. do_board_detect();
  477. #endif
  478. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  479. /* Enable RTC32K clock */
  480. rtc32k_enable();
  481. #endif
  482. }
  483. #ifdef CONFIG_SPL_BUILD
  484. void board_init_f(ulong dummy)
  485. {
  486. hw_data_init();
  487. early_system_init();
  488. board_early_init_f();
  489. sdram_init();
  490. /* dram_init must store complete ramsize in gd->ram_size */
  491. gd->ram_size = get_ram_size(
  492. (void *)CONFIG_SYS_SDRAM_BASE,
  493. CONFIG_MAX_RAM_BANK_SIZE);
  494. }
  495. #endif
  496. #endif
  497. int arch_cpu_init_dm(void)
  498. {
  499. hw_data_init();
  500. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  501. early_system_init();
  502. #endif
  503. return 0;
  504. }