cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <ahci.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <linux/bitops.h>
  10. #include <linux/delay.h>
  11. #include <linux/mbus.h>
  12. #include <asm/io.h>
  13. #include <asm/pl310.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/soc.h>
  16. #include <sdhci.h>
  17. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  18. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  19. static struct mbus_win windows[] = {
  20. /* SPI */
  21. { MBUS_SPI_BASE, MBUS_SPI_SIZE,
  22. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
  23. /* NOR */
  24. { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
  25. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
  26. #ifdef CONFIG_ARMADA_MSYS
  27. /* DFX */
  28. { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
  29. #endif
  30. };
  31. void lowlevel_init(void)
  32. {
  33. /*
  34. * Dummy implementation, we only need LOWLEVEL_INIT
  35. * on Armada to configure CP15 in start.S / cpu_init_cp15()
  36. */
  37. }
  38. void reset_cpu(unsigned long ignored)
  39. {
  40. struct mvebu_system_registers *reg =
  41. (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  42. writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  43. writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  44. while (1)
  45. ;
  46. }
  47. int mvebu_soc_family(void)
  48. {
  49. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  50. switch (devid) {
  51. case SOC_MV78230_ID:
  52. case SOC_MV78260_ID:
  53. case SOC_MV78460_ID:
  54. return MVEBU_SOC_AXP;
  55. case SOC_88F6720_ID:
  56. return MVEBU_SOC_A375;
  57. case SOC_88F6810_ID:
  58. case SOC_88F6820_ID:
  59. case SOC_88F6828_ID:
  60. return MVEBU_SOC_A38X;
  61. case SOC_98DX3236_ID:
  62. case SOC_98DX3336_ID:
  63. case SOC_98DX4251_ID:
  64. return MVEBU_SOC_MSYS;
  65. }
  66. return MVEBU_SOC_UNKNOWN;
  67. }
  68. #if defined(CONFIG_DISPLAY_CPUINFO)
  69. #if defined(CONFIG_ARMADA_375)
  70. /* SAR frequency values for Armada 375 */
  71. static const struct sar_freq_modes sar_freq_tab[] = {
  72. { 0, 0x0, 266, 133, 266 },
  73. { 1, 0x0, 333, 167, 167 },
  74. { 2, 0x0, 333, 167, 222 },
  75. { 3, 0x0, 333, 167, 333 },
  76. { 4, 0x0, 400, 200, 200 },
  77. { 5, 0x0, 400, 200, 267 },
  78. { 6, 0x0, 400, 200, 400 },
  79. { 7, 0x0, 500, 250, 250 },
  80. { 8, 0x0, 500, 250, 334 },
  81. { 9, 0x0, 500, 250, 500 },
  82. { 10, 0x0, 533, 267, 267 },
  83. { 11, 0x0, 533, 267, 356 },
  84. { 12, 0x0, 533, 267, 533 },
  85. { 13, 0x0, 600, 300, 300 },
  86. { 14, 0x0, 600, 300, 400 },
  87. { 15, 0x0, 600, 300, 600 },
  88. { 16, 0x0, 666, 333, 333 },
  89. { 17, 0x0, 666, 333, 444 },
  90. { 18, 0x0, 666, 333, 666 },
  91. { 19, 0x0, 800, 400, 267 },
  92. { 20, 0x0, 800, 400, 400 },
  93. { 21, 0x0, 800, 400, 534 },
  94. { 22, 0x0, 900, 450, 300 },
  95. { 23, 0x0, 900, 450, 450 },
  96. { 24, 0x0, 900, 450, 600 },
  97. { 25, 0x0, 1000, 500, 500 },
  98. { 26, 0x0, 1000, 500, 667 },
  99. { 27, 0x0, 1000, 333, 500 },
  100. { 28, 0x0, 400, 400, 400 },
  101. { 29, 0x0, 1100, 550, 550 },
  102. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  103. };
  104. #elif defined(CONFIG_ARMADA_38X)
  105. /* SAR frequency values for Armada 38x */
  106. static const struct sar_freq_modes sar_freq_tab[] = {
  107. { 0x0, 0x0, 666, 333, 333 },
  108. { 0x2, 0x0, 800, 400, 400 },
  109. { 0x4, 0x0, 1066, 533, 533 },
  110. { 0x6, 0x0, 1200, 600, 600 },
  111. { 0x8, 0x0, 1332, 666, 666 },
  112. { 0xc, 0x0, 1600, 800, 800 },
  113. { 0x10, 0x0, 1866, 933, 933 },
  114. { 0x13, 0x0, 2000, 1000, 933 },
  115. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  116. };
  117. #elif defined(CONFIG_ARMADA_MSYS)
  118. static const struct sar_freq_modes sar_freq_tab[] = {
  119. { 0x0, 0x0, 400, 400, 400 },
  120. { 0x2, 0x0, 667, 333, 667 },
  121. { 0x3, 0x0, 800, 400, 800 },
  122. { 0x5, 0x0, 800, 400, 800 },
  123. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  124. };
  125. #else
  126. /* SAR frequency values for Armada XP */
  127. static const struct sar_freq_modes sar_freq_tab[] = {
  128. { 0xa, 0x5, 800, 400, 400 },
  129. { 0x1, 0x5, 1066, 533, 533 },
  130. { 0x2, 0x5, 1200, 600, 600 },
  131. { 0x2, 0x9, 1200, 600, 400 },
  132. { 0x3, 0x5, 1333, 667, 667 },
  133. { 0x4, 0x5, 1500, 750, 750 },
  134. { 0x4, 0x9, 1500, 750, 500 },
  135. { 0xb, 0x9, 1600, 800, 533 },
  136. { 0xb, 0xa, 1600, 800, 640 },
  137. { 0xb, 0x5, 1600, 800, 800 },
  138. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  139. };
  140. #endif
  141. void get_sar_freq(struct sar_freq_modes *sar_freq)
  142. {
  143. u32 val;
  144. u32 freq;
  145. int i;
  146. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
  147. val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
  148. #else
  149. val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
  150. #endif
  151. freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
  152. #if defined(SAR2_CPU_FREQ_MASK)
  153. /*
  154. * Shift CPU0 clock frequency select bit from SAR2 register
  155. * into correct position
  156. */
  157. freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
  158. >> SAR2_CPU_FREQ_OFFS) << 3;
  159. #endif
  160. for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
  161. if (sar_freq_tab[i].val == freq) {
  162. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
  163. *sar_freq = sar_freq_tab[i];
  164. return;
  165. #else
  166. int k;
  167. u8 ffc;
  168. ffc = (val & SAR_FFC_FREQ_MASK) >>
  169. SAR_FFC_FREQ_OFFS;
  170. for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
  171. if (sar_freq_tab[k].ffc == ffc) {
  172. *sar_freq = sar_freq_tab[k];
  173. return;
  174. }
  175. }
  176. i = k;
  177. #endif
  178. }
  179. }
  180. /* SAR value not found, return 0 for frequencies */
  181. *sar_freq = sar_freq_tab[i - 1];
  182. }
  183. int print_cpuinfo(void)
  184. {
  185. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  186. u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
  187. struct sar_freq_modes sar_freq;
  188. puts("SoC: ");
  189. switch (devid) {
  190. case SOC_MV78230_ID:
  191. puts("MV78230-");
  192. break;
  193. case SOC_MV78260_ID:
  194. puts("MV78260-");
  195. break;
  196. case SOC_MV78460_ID:
  197. puts("MV78460-");
  198. break;
  199. case SOC_88F6720_ID:
  200. puts("MV88F6720-");
  201. break;
  202. case SOC_88F6810_ID:
  203. puts("MV88F6810-");
  204. break;
  205. case SOC_88F6820_ID:
  206. puts("MV88F6820-");
  207. break;
  208. case SOC_88F6828_ID:
  209. puts("MV88F6828-");
  210. break;
  211. case SOC_98DX3236_ID:
  212. puts("98DX3236-");
  213. break;
  214. case SOC_98DX3336_ID:
  215. puts("98DX3336-");
  216. break;
  217. case SOC_98DX4251_ID:
  218. puts("98DX4251-");
  219. break;
  220. default:
  221. puts("Unknown-");
  222. break;
  223. }
  224. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  225. switch (revid) {
  226. case 1:
  227. puts("A0");
  228. break;
  229. case 2:
  230. puts("B0");
  231. break;
  232. default:
  233. printf("?? (%x)", revid);
  234. break;
  235. }
  236. }
  237. if (mvebu_soc_family() == MVEBU_SOC_A375) {
  238. switch (revid) {
  239. case MV_88F67XX_A0_ID:
  240. puts("A0");
  241. break;
  242. default:
  243. printf("?? (%x)", revid);
  244. break;
  245. }
  246. }
  247. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  248. switch (revid) {
  249. case MV_88F68XX_Z1_ID:
  250. puts("Z1");
  251. break;
  252. case MV_88F68XX_A0_ID:
  253. puts("A0");
  254. break;
  255. case MV_88F68XX_B0_ID:
  256. puts("B0");
  257. break;
  258. default:
  259. printf("?? (%x)", revid);
  260. break;
  261. }
  262. }
  263. if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
  264. switch (revid) {
  265. case 3:
  266. puts("A0");
  267. break;
  268. case 4:
  269. puts("A1");
  270. break;
  271. default:
  272. printf("?? (%x)", revid);
  273. break;
  274. }
  275. }
  276. get_sar_freq(&sar_freq);
  277. printf(" at %d MHz\n", sar_freq.p_clk);
  278. return 0;
  279. }
  280. #endif /* CONFIG_DISPLAY_CPUINFO */
  281. /*
  282. * This function initialize Controller DRAM Fastpath windows.
  283. * It takes the CS size information from the 0x1500 scratch registers
  284. * and sets the correct windows sizes and base addresses accordingly.
  285. *
  286. * These values are set in the scratch registers by the Marvell
  287. * DDR3 training code, which is executed by the SPL before the
  288. * main payload (U-Boot) is executed.
  289. */
  290. static void update_sdram_window_sizes(void)
  291. {
  292. u64 base = 0;
  293. u32 size, temp;
  294. int i;
  295. for (i = 0; i < SDRAM_MAX_CS; i++) {
  296. size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
  297. if (size != 0) {
  298. size |= ~(SDRAM_ADDR_MASK);
  299. /* Set Base Address */
  300. temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
  301. writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
  302. /*
  303. * Check if out of max window size and resize
  304. * the window
  305. */
  306. temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
  307. ~(SDRAM_ADDR_MASK)) | 1;
  308. temp |= (size & SDRAM_ADDR_MASK);
  309. writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
  310. base += ((u64)size + 1);
  311. } else {
  312. /*
  313. * Disable window if not used, otherwise this
  314. * leads to overlapping enabled windows with
  315. * pretty strange results
  316. */
  317. clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
  318. }
  319. }
  320. }
  321. void mmu_disable(void)
  322. {
  323. asm volatile(
  324. "mrc p15, 0, r0, c1, c0, 0\n"
  325. "bic r0, #1\n"
  326. "mcr p15, 0, r0, c1, c0, 0\n");
  327. }
  328. #ifdef CONFIG_ARCH_CPU_INIT
  329. static void set_cbar(u32 addr)
  330. {
  331. asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
  332. }
  333. #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
  334. #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
  335. #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
  336. (((addr) & 0xF) << 6))
  337. #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
  338. (((reg) & 0xF) << 2))
  339. static void setup_usb_phys(void)
  340. {
  341. int dev;
  342. /*
  343. * USB PLL init
  344. */
  345. /* Setup PLL frequency */
  346. /* USB REF frequency = 25 MHz */
  347. clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
  348. /* Power up PLL and PHY channel */
  349. setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
  350. /* Assert VCOCAL_START */
  351. setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
  352. mdelay(1);
  353. /*
  354. * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
  355. */
  356. for (dev = 0; dev < 3; dev++) {
  357. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
  358. /* Assert REG_RCAL_START in channel REG 1 */
  359. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  360. udelay(40);
  361. clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  362. }
  363. }
  364. /*
  365. * This function is not called from the SPL U-Boot version
  366. */
  367. int arch_cpu_init(void)
  368. {
  369. struct pl310_regs *const pl310 =
  370. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  371. /*
  372. * Only with disabled MMU its possible to switch the base
  373. * register address on Armada 38x. Without this the SDRAM
  374. * located at >= 0x4000.0000 is also not accessible, as its
  375. * still locked to cache.
  376. */
  377. mmu_disable();
  378. /* Linux expects the internal registers to be at 0xf1000000 */
  379. writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
  380. set_cbar(SOC_REGS_PHY_BASE + 0xC000);
  381. /*
  382. * From this stage on, the SoC detection is working. As we have
  383. * configured the internal register base to the value used
  384. * in the macros / defines in the U-Boot header (soc.h).
  385. */
  386. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  387. /*
  388. * To fully release / unlock this area from cache, we need
  389. * to flush all caches and disable the L2 cache.
  390. */
  391. icache_disable();
  392. dcache_disable();
  393. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  394. }
  395. /*
  396. * We need to call mvebu_mbus_probe() before calling
  397. * update_sdram_window_sizes() as it disables all previously
  398. * configured mbus windows and then configures them as
  399. * required for U-Boot. Calling update_sdram_window_sizes()
  400. * without this configuration will not work, as the internal
  401. * registers can't be accessed reliably because of potenial
  402. * double mapping.
  403. * After updating the SDRAM access windows we need to call
  404. * mvebu_mbus_probe() again, as this now correctly configures
  405. * the SDRAM areas that are later used by the MVEBU drivers
  406. * (e.g. USB, NETA).
  407. */
  408. /*
  409. * First disable all windows
  410. */
  411. mvebu_mbus_probe(NULL, 0);
  412. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  413. /*
  414. * Now the SDRAM access windows can be reconfigured using
  415. * the information in the SDRAM scratch pad registers
  416. */
  417. update_sdram_window_sizes();
  418. }
  419. /*
  420. * Finally the mbus windows can be configured with the
  421. * updated SDRAM sizes
  422. */
  423. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  424. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  425. /* Enable GBE0, GBE1, LCD and NFC PUP */
  426. clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
  427. GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
  428. NAND_PUP_EN | SPI_PUP_EN);
  429. /* Configure USB PLL and PHYs on AXP */
  430. setup_usb_phys();
  431. }
  432. /* Enable NAND and NAND arbiter */
  433. clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
  434. /* Disable MBUS error propagation */
  435. clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
  436. return 0;
  437. }
  438. #endif /* CONFIG_ARCH_CPU_INIT */
  439. u32 mvebu_get_nand_clock(void)
  440. {
  441. u32 reg;
  442. if (mvebu_soc_family() == MVEBU_SOC_A38X)
  443. reg = MVEBU_DFX_DIV_CLK_CTRL(1);
  444. else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
  445. reg = MVEBU_DFX_DIV_CLK_CTRL(8);
  446. else
  447. reg = MVEBU_CORE_DIV_CLK_CTRL(1);
  448. return CONFIG_SYS_MVEBU_PLL_CLOCK /
  449. ((readl(reg) &
  450. NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
  451. }
  452. /*
  453. * SOC specific misc init
  454. */
  455. #if defined(CONFIG_ARCH_MISC_INIT)
  456. int arch_misc_init(void)
  457. {
  458. /* Nothing yet, perhaps we need something here later */
  459. return 0;
  460. }
  461. #endif /* CONFIG_ARCH_MISC_INIT */
  462. #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
  463. int board_mmc_init(struct bd_info *bis)
  464. {
  465. mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
  466. SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
  467. return 0;
  468. }
  469. #endif
  470. #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
  471. #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
  472. #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
  473. #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
  474. #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
  475. static void ahci_mvebu_mbus_config(void __iomem *base)
  476. {
  477. const struct mbus_dram_target_info *dram;
  478. int i;
  479. /* mbus is not initialized in SPL; keep the ROM settings */
  480. if (IS_ENABLED(CONFIG_SPL_BUILD))
  481. return;
  482. dram = mvebu_mbus_dram_info();
  483. for (i = 0; i < 4; i++) {
  484. writel(0, base + AHCI_WINDOW_CTRL(i));
  485. writel(0, base + AHCI_WINDOW_BASE(i));
  486. writel(0, base + AHCI_WINDOW_SIZE(i));
  487. }
  488. for (i = 0; i < dram->num_cs; i++) {
  489. const struct mbus_dram_window *cs = dram->cs + i;
  490. writel((cs->mbus_attr << 8) |
  491. (dram->mbus_dram_target_id << 4) | 1,
  492. base + AHCI_WINDOW_CTRL(i));
  493. writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
  494. writel(((cs->size - 1) & 0xffff0000),
  495. base + AHCI_WINDOW_SIZE(i));
  496. }
  497. }
  498. static void ahci_mvebu_regret_option(void __iomem *base)
  499. {
  500. /*
  501. * Enable the regret bit to allow the SATA unit to regret a
  502. * request that didn't receive an acknowlegde and avoid a
  503. * deadlock
  504. */
  505. writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
  506. writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
  507. }
  508. int board_ahci_enable(void)
  509. {
  510. ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
  511. ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
  512. return 0;
  513. }
  514. #ifdef CONFIG_SCSI_AHCI_PLAT
  515. void scsi_init(void)
  516. {
  517. printf("MVEBU SATA INIT\n");
  518. board_ahci_enable();
  519. ahci_init((void __iomem *)MVEBU_SATA0_BASE);
  520. }
  521. #endif
  522. #ifdef CONFIG_USB_XHCI_MVEBU
  523. #define USB3_MAX_WINDOWS 4
  524. #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
  525. #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
  526. static void xhci_mvebu_mbus_config(void __iomem *base,
  527. const struct mbus_dram_target_info *dram)
  528. {
  529. int i;
  530. for (i = 0; i < USB3_MAX_WINDOWS; i++) {
  531. writel(0, base + USB3_WIN_CTRL(i));
  532. writel(0, base + USB3_WIN_BASE(i));
  533. }
  534. for (i = 0; i < dram->num_cs; i++) {
  535. const struct mbus_dram_window *cs = dram->cs + i;
  536. /* Write size, attributes and target id to control register */
  537. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  538. (dram->mbus_dram_target_id << 4) | 1,
  539. base + USB3_WIN_CTRL(i));
  540. /* Write base address to base register */
  541. writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
  542. }
  543. }
  544. int board_xhci_enable(fdt_addr_t base)
  545. {
  546. const struct mbus_dram_target_info *dram;
  547. printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
  548. dram = mvebu_mbus_dram_info();
  549. xhci_mvebu_mbus_config((void __iomem *)base, dram);
  550. return 0;
  551. }
  552. #endif
  553. void enable_caches(void)
  554. {
  555. /* Avoid problem with e.g. neta ethernet driver */
  556. invalidate_dcache_all();
  557. /*
  558. * Armada 375 still has some problems with d-cache enabled in the
  559. * ethernet driver (mvpp2). So lets keep the d-cache disabled
  560. * until this is solved.
  561. */
  562. if (mvebu_soc_family() != MVEBU_SOC_A375) {
  563. /* Enable D-cache. I-cache is already enabled in start.S */
  564. dcache_enable();
  565. }
  566. }
  567. void v7_outer_cache_enable(void)
  568. {
  569. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  570. struct pl310_regs *const pl310 =
  571. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  572. u32 u;
  573. /* The L2 cache is already disabled at this point */
  574. /*
  575. * For Aurora cache in no outer mode, enable via the CP15
  576. * coprocessor broadcasting of cache commands to L2.
  577. */
  578. asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
  579. u |= BIT(8); /* Set the FW bit */
  580. asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
  581. isb();
  582. /* Enable the L2 cache */
  583. setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  584. }
  585. }
  586. void v7_outer_cache_disable(void)
  587. {
  588. struct pl310_regs *const pl310 =
  589. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  590. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  591. }