cpu.c 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/wdt.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/io.h>
  15. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  16. static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
  17. void reset_cpu(ulong addr)
  18. {
  19. /* Enable watchdog clock */
  20. setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
  21. /* To be compatible with the original U-Boot code:
  22. * addr: - 0: perform hard reset.
  23. * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
  24. if (addr == 0) {
  25. /* Reset pulse length is 13005 peripheral clock frames */
  26. writel(13000, &wdt->pulse);
  27. /* Force WDOG_RESET2 and RESOUT_N signal active */
  28. writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
  29. | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
  30. } else {
  31. /* Force match output active */
  32. writel(0x01, &wdt->emr);
  33. /* Internal reset on match output (no pulse on "RESOUT_N") */
  34. writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
  35. }
  36. while (1)
  37. /* NOP */;
  38. }
  39. #if defined(CONFIG_ARCH_CPU_INIT)
  40. int arch_cpu_init(void)
  41. {
  42. /*
  43. * It might be necessary to flush data cache, if U-Boot is loaded
  44. * from kickstart bootloader, e.g. from S1L loader
  45. */
  46. flush_dcache_all();
  47. return 0;
  48. }
  49. #else
  50. #error "You have to select CONFIG_ARCH_CPU_INIT"
  51. #endif
  52. #if defined(CONFIG_DISPLAY_CPUINFO)
  53. int print_cpuinfo(void)
  54. {
  55. printf("CPU: NXP LPC32XX\n");
  56. printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
  57. printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
  58. printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
  59. return 0;
  60. }
  61. #endif
  62. #ifdef CONFIG_LPC32XX_ETH
  63. int cpu_eth_init(struct bd_info *bis)
  64. {
  65. lpc32xx_eth_initialize(bis);
  66. return 0;
  67. }
  68. #endif