clk.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <div64.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/io.h>
  11. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  12. unsigned int get_sys_clk_rate(void)
  13. {
  14. if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
  15. return RTC_CLK_FREQUENCY * 397;
  16. else
  17. return OSC_CLK_FREQUENCY;
  18. }
  19. unsigned int get_hclk_pll_rate(void)
  20. {
  21. unsigned long long fin, fref, fcco, fout;
  22. u32 val, m_div, n_div, p_div;
  23. /*
  24. * Valid frequency ranges:
  25. * 1 * 10^6 <= Fin <= 20 * 10^6
  26. * 1 * 10^6 <= Fref <= 27 * 10^6
  27. * 156 * 10^6 <= Fcco <= 320 * 10^6
  28. */
  29. fref = fin = get_sys_clk_rate();
  30. if (fin > 20000000ULL || fin < 1000000ULL)
  31. return 0;
  32. val = readl(&clk->hclkpll_ctrl);
  33. m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
  34. n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
  35. if (val & CLK_HCLK_PLL_DIRECT)
  36. p_div = 0;
  37. else
  38. p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
  39. p_div = 1 << p_div;
  40. if (val & CLK_HCLK_PLL_BYPASS) {
  41. do_div(fin, p_div);
  42. return fin;
  43. }
  44. do_div(fref, n_div);
  45. if (fref > 27000000ULL || fref < 1000000ULL)
  46. return 0;
  47. fcco = fref * m_div;
  48. fout = fcco;
  49. if (val & CLK_HCLK_PLL_FEEDBACK)
  50. fcco *= p_div;
  51. else
  52. do_div(fout, p_div);
  53. if (fcco > 320000000ULL || fcco < 156000000ULL)
  54. return 0;
  55. return fout;
  56. }
  57. unsigned int get_hclk_clk_div(void)
  58. {
  59. u32 val;
  60. val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
  61. return 1 << val;
  62. }
  63. unsigned int get_hclk_clk_rate(void)
  64. {
  65. return get_hclk_pll_rate() / get_hclk_clk_div();
  66. }
  67. unsigned int get_periph_clk_div(void)
  68. {
  69. u32 val;
  70. val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
  71. return (val >> 2) + 1;
  72. }
  73. unsigned int get_periph_clk_rate(void)
  74. {
  75. if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
  76. return get_sys_clk_rate();
  77. return get_hclk_pll_rate() / get_periph_clk_div();
  78. }
  79. unsigned int get_sdram_clk_rate(void)
  80. {
  81. unsigned int src_clk;
  82. if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
  83. return get_sys_clk_rate();
  84. src_clk = get_hclk_pll_rate();
  85. if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
  86. /* using DDR */
  87. switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
  88. case CLK_HCLK_DDRAM_HALF:
  89. return src_clk/2;
  90. case CLK_HCLK_DDRAM_NOMINAL:
  91. return src_clk;
  92. default:
  93. return 0;
  94. }
  95. } else {
  96. /* using SDR */
  97. switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
  98. case CLK_HCLK_ARM_PLL_DIV_4:
  99. return src_clk/4;
  100. case CLK_HCLK_ARM_PLL_DIV_2:
  101. return src_clk/2;
  102. case CLK_HCLK_ARM_PLL_DIV_1:
  103. return src_clk;
  104. default:
  105. return 0;
  106. }
  107. }
  108. }
  109. int get_serial_clock(void)
  110. {
  111. return get_periph_clk_rate();
  112. }