cpu.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <cpu_func.h>
  10. #include <env.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <asm/cache.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/soc.h>
  19. #include <mvebu_mmc.h>
  20. void reset_cpu(unsigned long ignored)
  21. {
  22. struct kwcpu_registers *cpureg =
  23. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  24. writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  25. &cpureg->rstoutn_mask);
  26. writel(readl(&cpureg->sys_soft_rst) | 1,
  27. &cpureg->sys_soft_rst);
  28. while (1) ;
  29. }
  30. /*
  31. * Window Size
  32. * Used with the Base register to set the address window size and location.
  33. * Must be programmed from LSB to MSB as sequence of ones followed by
  34. * sequence of zeros. The number of ones specifies the size of the window in
  35. * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  36. * NOTE: A value of 0x0 specifies 64-KByte size.
  37. */
  38. unsigned int kw_winctrl_calcsize(unsigned int sizeval)
  39. {
  40. int i;
  41. unsigned int j = 0;
  42. u32 val = sizeval >> 1;
  43. for (i = 0; val >= 0x10000; i++) {
  44. j |= (1 << i);
  45. val = val >> 1;
  46. }
  47. return (0x0000ffff & j);
  48. }
  49. static struct mbus_win windows[] = {
  50. /* Window 0: PCIE MEM address space */
  51. { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
  52. KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
  53. /* Window 1: PCIE IO address space */
  54. { KW_DEFADR_PCI_IO, 1024 * 64,
  55. KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
  56. /* Window 2: NAND Flash address space */
  57. { KW_DEFADR_NANDF, 1024 * 1024 * 128,
  58. KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
  59. /* Window 3: SPI Flash address space */
  60. { KW_DEFADR_SPIF, 1024 * 1024 * 128,
  61. KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
  62. /* Window 4: BOOT Memory address space */
  63. { KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
  64. KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
  65. /* Window 5: Security SRAM address space */
  66. { KW_DEFADR_SASRAM, 1024 * 64,
  67. KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
  68. };
  69. /*
  70. * SYSRSTn Duration Counter Support
  71. *
  72. * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
  73. * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
  74. * The SYSRSTn duration counter is useful for implementing a manufacturer
  75. * or factory reset. Upon a long reset assertion that is greater than a
  76. * pre-configured environment variable value for sysrstdelay,
  77. * The counter value is stored in the SYSRSTn Length Counter Register
  78. * The counter is based on the 25-MHz reference clock (40ns)
  79. * It is a 29-bit counter, yielding a maximum counting duration of
  80. * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
  81. * it remains at this value until counter reset is triggered by setting
  82. * bit 31 of KW_REG_SYSRST_CNT
  83. */
  84. static void kw_sysrst_action(void)
  85. {
  86. int ret;
  87. char *s = env_get("sysrstcmd");
  88. if (!s) {
  89. debug("Error.. %s failed, check sysrstcmd\n",
  90. __FUNCTION__);
  91. return;
  92. }
  93. debug("Starting %s process...\n", __FUNCTION__);
  94. ret = run_command(s, 0);
  95. if (ret != 0)
  96. debug("Error.. %s failed\n", __FUNCTION__);
  97. else
  98. debug("%s process finished\n", __FUNCTION__);
  99. }
  100. static void kw_sysrst_check(void)
  101. {
  102. u32 sysrst_cnt, sysrst_dly;
  103. char *s;
  104. /*
  105. * no action if sysrstdelay environment variable is not defined
  106. */
  107. s = env_get("sysrstdelay");
  108. if (s == NULL)
  109. return;
  110. /* read sysrstdelay value */
  111. sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
  112. /* read SysRst Length counter register (bits 28:0) */
  113. sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
  114. debug("H/w Rst hold time: %d.%d secs\n",
  115. sysrst_cnt / SYSRST_CNT_1SEC_VAL,
  116. sysrst_cnt % SYSRST_CNT_1SEC_VAL);
  117. /* clear the counter for next valid read*/
  118. writel(1 << 31, KW_REG_SYSRST_CNT);
  119. /*
  120. * sysrst_action:
  121. * if H/w Reset key is pressed and hold for time
  122. * more than sysrst_dly in seconds
  123. */
  124. if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
  125. kw_sysrst_action();
  126. }
  127. #if defined(CONFIG_DISPLAY_CPUINFO)
  128. int print_cpuinfo(void)
  129. {
  130. char *rev = "??";
  131. u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
  132. u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
  133. if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
  134. printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
  135. return -1;
  136. }
  137. switch (revid) {
  138. case 0:
  139. if (devid == 0x6281)
  140. rev = "Z0";
  141. else if (devid == 0x6282)
  142. rev = "A0";
  143. break;
  144. case 1:
  145. rev = "A1";
  146. break;
  147. case 2:
  148. rev = "A0";
  149. break;
  150. case 3:
  151. rev = "A1";
  152. break;
  153. default:
  154. break;
  155. }
  156. printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
  157. return 0;
  158. }
  159. #endif /* CONFIG_DISPLAY_CPUINFO */
  160. #ifdef CONFIG_ARCH_CPU_INIT
  161. int arch_cpu_init(void)
  162. {
  163. u32 reg;
  164. struct kwcpu_registers *cpureg =
  165. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  166. /* Linux expects the internal registers to be at 0xf1000000 */
  167. writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
  168. /* Enable and invalidate L2 cache in write through mode */
  169. writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
  170. invalidate_l2_cache();
  171. #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
  172. /*
  173. * Configures the I/O voltage of the pads connected to Egigabit
  174. * Ethernet interface to 1.8V
  175. * By default it is set to 3.3V
  176. */
  177. reg = readl(KW_REG_MPP_OUT_DRV_REG);
  178. reg |= (1 << 7);
  179. writel(reg, KW_REG_MPP_OUT_DRV_REG);
  180. #endif
  181. #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
  182. /*
  183. * Set egiga port0/1 in normal functional mode
  184. * This is required becasue on kirkwood by default ports are in reset mode
  185. * OS egiga driver may not have provision to set them in normal mode
  186. * and if u-boot is build without network support, network may fail at OS level
  187. */
  188. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
  189. reg &= ~(1 << 4); /* Clear PortReset Bit */
  190. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
  191. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
  192. reg &= ~(1 << 4); /* Clear PortReset Bit */
  193. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
  194. #endif
  195. #ifdef CONFIG_KIRKWOOD_PCIE_INIT
  196. /*
  197. * Enable PCI Express Port0
  198. */
  199. reg = readl(&cpureg->ctrl_stat);
  200. reg |= (1 << 0); /* Set PEX0En Bit */
  201. writel(reg, &cpureg->ctrl_stat);
  202. #endif
  203. return 0;
  204. }
  205. #endif /* CONFIG_ARCH_CPU_INIT */
  206. /*
  207. * SOC specific misc init
  208. */
  209. #if defined(CONFIG_ARCH_MISC_INIT)
  210. int arch_misc_init(void)
  211. {
  212. volatile u32 temp;
  213. /*CPU streaming & write allocate */
  214. temp = readfr_extra_feature_reg();
  215. temp &= ~(1 << 28); /* disable wr alloc */
  216. writefr_extra_feature_reg(temp);
  217. temp = readfr_extra_feature_reg();
  218. temp &= ~(1 << 29); /* streaming disabled */
  219. writefr_extra_feature_reg(temp);
  220. /* L2Cache settings */
  221. temp = readfr_extra_feature_reg();
  222. /* Disable L2C pre fetch - Set bit 24 */
  223. temp |= (1 << 24);
  224. /* enable L2C - Set bit 22 */
  225. temp |= (1 << 22);
  226. writefr_extra_feature_reg(temp);
  227. /* Change reset vector to address 0x0 */
  228. temp = get_cr();
  229. set_cr(temp & ~CR_V);
  230. /* Configure mbus windows */
  231. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  232. /* checks and execute resset to factory event */
  233. kw_sysrst_check();
  234. return 0;
  235. }
  236. #endif /* CONFIG_ARCH_MISC_INIT */
  237. #ifdef CONFIG_MVGBE
  238. int cpu_eth_init(struct bd_info *bis)
  239. {
  240. mvgbe_initialize(bis);
  241. return 0;
  242. }
  243. #endif
  244. #ifdef CONFIG_MVEBU_MMC
  245. int board_mmc_init(struct bd_info *bis)
  246. {
  247. mvebu_mmc_init(bis);
  248. return 0;
  249. }
  250. #endif /* CONFIG_MVEBU_MMC */