soc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/bootm.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/dma.h>
  19. #include <asm/mach-imx/hab.h>
  20. #include <stdbool.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/crm_regs.h>
  23. #include <dm.h>
  24. #include <fsl_sec.h>
  25. #include <imx_thermal.h>
  26. #include <mmc.h>
  27. struct scu_regs {
  28. u32 ctrl;
  29. u32 config;
  30. u32 status;
  31. u32 invalidate;
  32. u32 fpga_rev;
  33. };
  34. #if defined(CONFIG_IMX_THERMAL)
  35. static const struct imx_thermal_plat imx6_thermal_plat = {
  36. .regs = (void *)ANATOP_BASE_ADDR,
  37. .fuse_bank = 1,
  38. .fuse_word = 6,
  39. };
  40. U_BOOT_DEVICE(imx6_thermal) = {
  41. .name = "imx_thermal",
  42. .platdata = &imx6_thermal_plat,
  43. };
  44. #endif
  45. #if defined(CONFIG_IMX_HAB)
  46. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  47. .bank = 0,
  48. .word = 6,
  49. };
  50. #endif
  51. u32 get_nr_cpus(void)
  52. {
  53. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  54. return readl(&scu->config) & 3;
  55. }
  56. u32 get_cpu_rev(void)
  57. {
  58. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  59. u32 reg = readl(&anatop->digprog_sololite);
  60. u32 type = ((reg >> 16) & 0xff);
  61. u32 major, cfg = 0;
  62. if (type != MXC_CPU_MX6SL) {
  63. reg = readl(&anatop->digprog);
  64. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  65. cfg = readl(&scu->config) & 3;
  66. type = ((reg >> 16) & 0xff);
  67. if (type == MXC_CPU_MX6DL) {
  68. if (!cfg)
  69. type = MXC_CPU_MX6SOLO;
  70. }
  71. if (type == MXC_CPU_MX6Q) {
  72. if (cfg == 1)
  73. type = MXC_CPU_MX6D;
  74. }
  75. if (type == MXC_CPU_MX6ULL) {
  76. if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
  77. type = MXC_CPU_MX6ULZ;
  78. }
  79. }
  80. major = ((reg >> 8) & 0xff);
  81. if ((major >= 1) &&
  82. ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  83. major--;
  84. type = MXC_CPU_MX6QP;
  85. if (cfg == 1)
  86. type = MXC_CPU_MX6DP;
  87. }
  88. reg &= 0xff; /* mx6 silicon revision */
  89. /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
  90. if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
  91. reg = 0x3;
  92. return (type << 12) | (reg + (0x10 * (major + 1)));
  93. }
  94. /*
  95. * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
  96. * defines a 2-bit SPEED_GRADING
  97. */
  98. #define OCOTP_CFG3_SPEED_SHIFT 16
  99. #define OCOTP_CFG3_SPEED_800MHZ 0
  100. #define OCOTP_CFG3_SPEED_850MHZ 1
  101. #define OCOTP_CFG3_SPEED_1GHZ 2
  102. #define OCOTP_CFG3_SPEED_1P2GHZ 3
  103. /*
  104. * For i.MX6UL
  105. */
  106. #define OCOTP_CFG3_SPEED_528MHZ 1
  107. #define OCOTP_CFG3_SPEED_696MHZ 2
  108. /*
  109. * For i.MX6ULL
  110. */
  111. #define OCOTP_CFG3_SPEED_792MHZ 2
  112. #define OCOTP_CFG3_SPEED_900MHZ 3
  113. u32 get_cpu_speed_grade_hz(void)
  114. {
  115. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  116. struct fuse_bank *bank = &ocotp->bank[0];
  117. struct fuse_bank0_regs *fuse =
  118. (struct fuse_bank0_regs *)bank->fuse_regs;
  119. uint32_t val;
  120. val = readl(&fuse->cfg3);
  121. val >>= OCOTP_CFG3_SPEED_SHIFT;
  122. val &= 0x3;
  123. if (is_mx6ul()) {
  124. if (val == OCOTP_CFG3_SPEED_528MHZ)
  125. return 528000000;
  126. else if (val == OCOTP_CFG3_SPEED_696MHZ)
  127. return 696000000;
  128. else
  129. return 0;
  130. }
  131. if (is_mx6ull()) {
  132. if (val == OCOTP_CFG3_SPEED_528MHZ)
  133. return 528000000;
  134. else if (val == OCOTP_CFG3_SPEED_792MHZ)
  135. return 792000000;
  136. else if (val == OCOTP_CFG3_SPEED_900MHZ)
  137. return 900000000;
  138. else
  139. return 0;
  140. }
  141. switch (val) {
  142. /* Valid for IMX6DQ */
  143. case OCOTP_CFG3_SPEED_1P2GHZ:
  144. if (is_mx6dq() || is_mx6dqp())
  145. return 1200000000;
  146. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  147. case OCOTP_CFG3_SPEED_1GHZ:
  148. return 996000000;
  149. /* Valid for IMX6DQ */
  150. case OCOTP_CFG3_SPEED_850MHZ:
  151. if (is_mx6dq() || is_mx6dqp())
  152. return 852000000;
  153. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  154. case OCOTP_CFG3_SPEED_800MHZ:
  155. return 792000000;
  156. }
  157. return 0;
  158. }
  159. /*
  160. * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
  161. * defines a 2-bit Temperature Grade
  162. *
  163. * return temperature grade and min/max temperature in Celsius
  164. */
  165. #define OCOTP_MEM0_TEMP_SHIFT 6
  166. u32 get_cpu_temp_grade(int *minc, int *maxc)
  167. {
  168. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  169. struct fuse_bank *bank = &ocotp->bank[1];
  170. struct fuse_bank1_regs *fuse =
  171. (struct fuse_bank1_regs *)bank->fuse_regs;
  172. uint32_t val;
  173. val = readl(&fuse->mem0);
  174. val >>= OCOTP_MEM0_TEMP_SHIFT;
  175. val &= 0x3;
  176. if (minc && maxc) {
  177. if (val == TEMP_AUTOMOTIVE) {
  178. *minc = -40;
  179. *maxc = 125;
  180. } else if (val == TEMP_INDUSTRIAL) {
  181. *minc = -40;
  182. *maxc = 105;
  183. } else if (val == TEMP_EXTCOMMERCIAL) {
  184. *minc = -20;
  185. *maxc = 105;
  186. } else {
  187. *minc = 0;
  188. *maxc = 95;
  189. }
  190. }
  191. return val;
  192. }
  193. #ifdef CONFIG_REVISION_TAG
  194. u32 __weak get_board_rev(void)
  195. {
  196. u32 cpurev = get_cpu_rev();
  197. u32 type = ((cpurev >> 12) & 0xff);
  198. if (type == MXC_CPU_MX6SOLO)
  199. cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  200. if (type == MXC_CPU_MX6D)
  201. cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  202. return cpurev;
  203. }
  204. #endif
  205. static void clear_ldo_ramp(void)
  206. {
  207. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  208. int reg;
  209. /* ROM may modify LDO ramp up time according to fuse setting, so in
  210. * order to be in the safe side we neeed to reset these settings to
  211. * match the reset value: 0'b00
  212. */
  213. reg = readl(&anatop->ana_misc2);
  214. reg &= ~(0x3f << 24);
  215. writel(reg, &anatop->ana_misc2);
  216. }
  217. /*
  218. * Set the PMU_REG_CORE register
  219. *
  220. * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
  221. * Possible values are from 0.725V to 1.450V in steps of
  222. * 0.025V (25mV).
  223. */
  224. int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
  225. {
  226. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  227. u32 val, step, old, reg = readl(&anatop->reg_core);
  228. u8 shift;
  229. /* No LDO_SOC/PU/ARM */
  230. if (is_mx6sll())
  231. return 0;
  232. if (mv < 725)
  233. val = 0x00; /* Power gated off */
  234. else if (mv > 1450)
  235. val = 0x1F; /* Power FET switched full on. No regulation */
  236. else
  237. val = (mv - 700) / 25;
  238. clear_ldo_ramp();
  239. switch (ldo) {
  240. case LDO_SOC:
  241. shift = 18;
  242. break;
  243. case LDO_PU:
  244. shift = 9;
  245. break;
  246. case LDO_ARM:
  247. shift = 0;
  248. break;
  249. default:
  250. return -EINVAL;
  251. }
  252. old = (reg & (0x1F << shift)) >> shift;
  253. step = abs(val - old);
  254. if (step == 0)
  255. return 0;
  256. reg = (reg & ~(0x1F << shift)) | (val << shift);
  257. writel(reg, &anatop->reg_core);
  258. /*
  259. * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
  260. * step
  261. */
  262. udelay(3 * step);
  263. return 0;
  264. }
  265. static void set_ahb_rate(u32 val)
  266. {
  267. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  268. u32 reg, div;
  269. div = get_periph_clk() / val - 1;
  270. reg = readl(&mxc_ccm->cbcdr);
  271. writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
  272. (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
  273. }
  274. static void clear_mmdc_ch_mask(void)
  275. {
  276. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  277. u32 reg;
  278. reg = readl(&mxc_ccm->ccdr);
  279. /* Clear MMDC channel mask */
  280. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
  281. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
  282. else
  283. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
  284. writel(reg, &mxc_ccm->ccdr);
  285. }
  286. #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
  287. static void init_bandgap(void)
  288. {
  289. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  290. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  291. struct fuse_bank *bank = &ocotp->bank[1];
  292. struct fuse_bank1_regs *fuse =
  293. (struct fuse_bank1_regs *)bank->fuse_regs;
  294. uint32_t val;
  295. /*
  296. * Ensure the bandgap has stabilized.
  297. */
  298. while (!(readl(&anatop->ana_misc0) & 0x80))
  299. ;
  300. /*
  301. * For best noise performance of the analog blocks using the
  302. * outputs of the bandgap, the reftop_selfbiasoff bit should
  303. * be set.
  304. */
  305. writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
  306. /*
  307. * On i.MX6ULL,we need to set VBGADJ bits according to the
  308. * REFTOP_TRIM[3:0] in fuse table
  309. * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
  310. * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
  311. * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
  312. * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
  313. * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
  314. * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
  315. * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
  316. * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
  317. */
  318. if (is_mx6ull()) {
  319. val = readl(&fuse->mem0);
  320. val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
  321. val &= 0x7;
  322. writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
  323. &anatop->ana_misc0_set);
  324. }
  325. }
  326. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  327. static void noc_setup(void)
  328. {
  329. enable_ipu_clock();
  330. writel(0x80000201, 0xbb0608);
  331. /* Bypass IPU1 QoS generator */
  332. writel(0x00000002, 0x00bb048c);
  333. /* Bypass IPU2 QoS generator */
  334. writel(0x00000002, 0x00bb050c);
  335. /* Bandwidth THR for of PRE0 */
  336. writel(0x00000200, 0x00bb0690);
  337. /* Bandwidth THR for of PRE1 */
  338. writel(0x00000200, 0x00bb0710);
  339. /* Bandwidth THR for of PRE2 */
  340. writel(0x00000200, 0x00bb0790);
  341. /* Bandwidth THR for of PRE3 */
  342. writel(0x00000200, 0x00bb0810);
  343. /* Saturation THR for of PRE0 */
  344. writel(0x00000010, 0x00bb0694);
  345. /* Saturation THR for of PRE1 */
  346. writel(0x00000010, 0x00bb0714);
  347. /* Saturation THR for of PRE2 */
  348. writel(0x00000010, 0x00bb0794);
  349. /* Saturation THR for of PRE */
  350. writel(0x00000010, 0x00bb0814);
  351. disable_ipu_clock();
  352. }
  353. #endif
  354. int arch_cpu_init(void)
  355. {
  356. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  357. init_aips();
  358. /* Need to clear MMDC_CHx_MASK to make warm reset work. */
  359. clear_mmdc_ch_mask();
  360. /*
  361. * Disable self-bias circuit in the analog bandap.
  362. * The self-bias circuit is used by the bandgap during startup.
  363. * This bit should be set after the bandgap has initialized.
  364. */
  365. init_bandgap();
  366. if (!is_mx6ul() && !is_mx6ull()) {
  367. /*
  368. * When low freq boot is enabled, ROM will not set AHB
  369. * freq, so we need to ensure AHB freq is 132MHz in such
  370. * scenario.
  371. *
  372. * To i.MX6UL, when power up, default ARM core and
  373. * AHB rate is 396M and 132M.
  374. */
  375. if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
  376. set_ahb_rate(132000000);
  377. }
  378. if (is_mx6ul()) {
  379. if (is_soc_rev(CHIP_REV_1_0) == 0) {
  380. /*
  381. * According to the design team's requirement on
  382. * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
  383. * as open drain 100K (0x0000b8a0).
  384. * Only exists on TO1.0
  385. */
  386. writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
  387. } else {
  388. /*
  389. * From TO1.1, SNVS adds internal pull up control
  390. * for POR_B, the register filed is GPBIT[1:0],
  391. * after system boot up, it can be set to 2b'01
  392. * to disable internal pull up.It can save about
  393. * 30uA power in SNVS mode.
  394. */
  395. writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
  396. (~0x1400)) | 0x400,
  397. MX6UL_SNVS_LP_BASE_ADDR + 0x10);
  398. }
  399. }
  400. if (is_mx6ull()) {
  401. /*
  402. * GPBIT[1:0] is suggested to set to 2'b11:
  403. * 2'b00 : always PUP100K
  404. * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
  405. * 2'b10 : always disable PUP100K
  406. * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
  407. * register offset is different from i.MX6UL, since
  408. * i.MX6UL is fixed by ECO.
  409. */
  410. writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
  411. 0x3, MX6UL_SNVS_LP_BASE_ADDR);
  412. }
  413. /* Set perclk to source from OSC 24MHz */
  414. if (is_mx6sl())
  415. setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
  416. imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
  417. if (is_mx6sx())
  418. setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
  419. init_src();
  420. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  421. if (is_mx6dqp())
  422. noc_setup();
  423. #endif
  424. return 0;
  425. }
  426. #ifdef CONFIG_ENV_IS_IN_MMC
  427. __weak int board_mmc_get_env_dev(int devno)
  428. {
  429. return CONFIG_SYS_MMC_ENV_DEV;
  430. }
  431. static int mmc_get_boot_dev(void)
  432. {
  433. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  434. u32 soc_sbmr = readl(&src_regs->sbmr1);
  435. u32 bootsel;
  436. int devno;
  437. /*
  438. * Refer to
  439. * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
  440. * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
  441. * i.MX6SL/SX/UL has same layout.
  442. */
  443. bootsel = (soc_sbmr & 0x000000FF) >> 6;
  444. /* No boot from sd/mmc */
  445. if (bootsel != 1)
  446. return -1;
  447. /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  448. devno = (soc_sbmr & 0x00001800) >> 11;
  449. return devno;
  450. }
  451. int mmc_get_env_dev(void)
  452. {
  453. int devno = mmc_get_boot_dev();
  454. /* If not boot from sd/mmc, use default value */
  455. if (devno < 0)
  456. return CONFIG_SYS_MMC_ENV_DEV;
  457. return board_mmc_get_env_dev(devno);
  458. }
  459. #ifdef CONFIG_SYS_MMC_ENV_PART
  460. __weak int board_mmc_get_env_part(int devno)
  461. {
  462. return CONFIG_SYS_MMC_ENV_PART;
  463. }
  464. uint mmc_get_env_part(struct mmc *mmc)
  465. {
  466. int devno = mmc_get_boot_dev();
  467. /* If not boot from sd/mmc, use default value */
  468. if (devno < 0)
  469. return CONFIG_SYS_MMC_ENV_PART;
  470. return board_mmc_get_env_part(devno);
  471. }
  472. #endif
  473. #endif
  474. int board_postclk_init(void)
  475. {
  476. /* NO LDO SOC on i.MX6SLL */
  477. if (is_mx6sll())
  478. return 0;
  479. set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
  480. return 0;
  481. }
  482. #ifndef CONFIG_SPL_BUILD
  483. /*
  484. * cfg_val will be used for
  485. * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  486. * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
  487. * instead of SBMR1 to determine the boot device.
  488. */
  489. const struct boot_mode soc_boot_modes[] = {
  490. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  491. /* reserved value should start rom usb */
  492. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  493. {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  494. #else
  495. {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  496. #endif
  497. {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  498. {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  499. {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  500. {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  501. {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  502. /* 4 bit bus width */
  503. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  504. {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  505. {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  506. {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  507. {NULL, 0},
  508. };
  509. #endif
  510. void reset_misc(void)
  511. {
  512. #ifndef CONFIG_SPL_BUILD
  513. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  514. lcdif_power_down();
  515. #endif
  516. #endif
  517. }
  518. void s_init(void)
  519. {
  520. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  521. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  522. u32 mask480;
  523. u32 mask528;
  524. u32 reg, periph1, periph2;
  525. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
  526. return;
  527. /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
  528. * to make sure PFD is working right, otherwise, PFDs may
  529. * not output clock after reset, MX6DL and MX6SL have added 396M pfd
  530. * workaround in ROM code, as bus clock need it
  531. */
  532. mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
  533. ANATOP_PFD_CLKGATE_MASK(1) |
  534. ANATOP_PFD_CLKGATE_MASK(2) |
  535. ANATOP_PFD_CLKGATE_MASK(3);
  536. mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
  537. ANATOP_PFD_CLKGATE_MASK(3);
  538. reg = readl(&ccm->cbcmr);
  539. periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
  540. >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
  541. periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
  542. >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
  543. /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
  544. if ((periph2 != 0x2) && (periph1 != 0x2))
  545. mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
  546. if ((periph2 != 0x1) && (periph1 != 0x1) &&
  547. (periph2 != 0x3) && (periph1 != 0x3))
  548. mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
  549. writel(mask480, &anatop->pfd_480_set);
  550. writel(mask528, &anatop->pfd_528_set);
  551. writel(mask480, &anatop->pfd_480_clr);
  552. writel(mask528, &anatop->pfd_528_clr);
  553. }
  554. #ifdef CONFIG_IMX_HDMI
  555. void imx_enable_hdmi_phy(void)
  556. {
  557. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  558. u8 reg;
  559. reg = readb(&hdmi->phy_conf0);
  560. reg |= HDMI_PHY_CONF0_PDZ_MASK;
  561. writeb(reg, &hdmi->phy_conf0);
  562. udelay(3000);
  563. reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
  564. writeb(reg, &hdmi->phy_conf0);
  565. udelay(3000);
  566. reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
  567. writeb(reg, &hdmi->phy_conf0);
  568. writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
  569. }
  570. void imx_setup_hdmi(void)
  571. {
  572. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  573. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  574. int reg, count;
  575. u8 val;
  576. /* Turn on HDMI PHY clock */
  577. reg = readl(&mxc_ccm->CCGR2);
  578. reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
  579. MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
  580. writel(reg, &mxc_ccm->CCGR2);
  581. writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
  582. reg = readl(&mxc_ccm->chsccdr);
  583. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
  584. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
  585. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  586. reg |= (CHSCCDR_PODF_DIVIDE_BY_3
  587. << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
  588. |(CHSCCDR_IPU_PRE_CLK_540M_PFD
  589. << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  590. writel(reg, &mxc_ccm->chsccdr);
  591. /* Clear the overflow condition */
  592. if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
  593. /* TMDS software reset */
  594. writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
  595. val = readb(&hdmi->fc_invidconf);
  596. /* Need minimum 3 times to write to clear the register */
  597. for (count = 0 ; count < 5 ; count++)
  598. writeb(val, &hdmi->fc_invidconf);
  599. }
  600. }
  601. #endif
  602. #ifdef CONFIG_ARCH_MISC_INIT
  603. int arch_misc_init(void)
  604. {
  605. #ifdef CONFIG_FSL_CAAM
  606. sec_init();
  607. #endif
  608. return 0;
  609. }
  610. #endif
  611. /*
  612. * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
  613. * MX6Q and MX6QP processors
  614. */
  615. void gpr_init(void)
  616. {
  617. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  618. /*
  619. * If this function is used in a common MX6 spl implementation
  620. * we have to ensure that it is only called for suitable cpu types,
  621. * otherwise it breaks hardware parts like enet1, can1, can2, etc.
  622. */
  623. if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
  624. return;
  625. /* enable AXI cache for VDOA/VPU/IPU */
  626. writel(0xF00000CF, &iomux->gpr[4]);
  627. if (is_mx6dqp()) {
  628. /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
  629. writel(0x77177717, &iomux->gpr[6]);
  630. writel(0x77177717, &iomux->gpr[7]);
  631. } else {
  632. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  633. writel(0x007F007F, &iomux->gpr[6]);
  634. writel(0x007F007F, &iomux->gpr[7]);
  635. }
  636. }