litesom.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2016 Grinn
  5. */
  6. #include <init.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/iomux.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/mx6ul_pins.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/io.h>
  18. #include <common.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <linux/delay.h>
  21. #include <linux/sizes.h>
  22. #include <mmc.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  25. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  26. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  27. int dram_init(void)
  28. {
  29. gd->ram_size = imx_ddr_size();
  30. return 0;
  31. }
  32. static iomux_v3_cfg_t const emmc_pads[] = {
  33. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  34. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  35. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  36. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  37. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  38. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  39. MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  40. MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  41. MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  42. MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  43. /* RST_B */
  44. MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  45. };
  46. #ifdef CONFIG_FSL_ESDHC_IMX
  47. static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
  48. #define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
  49. int litesom_mmc_init(struct bd_info *bis)
  50. {
  51. int ret;
  52. /* eMMC */
  53. imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
  54. gpio_direction_output(EMMC_PWR_GPIO, 0);
  55. udelay(500);
  56. gpio_direction_output(EMMC_PWR_GPIO, 1);
  57. emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  58. ret = fsl_esdhc_initialize(bis, &emmc_cfg);
  59. if (ret) {
  60. printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
  61. return ret;
  62. }
  63. return 0;
  64. }
  65. #endif
  66. #ifdef CONFIG_SPL_BUILD
  67. #include <linux/libfdt.h>
  68. #include <spl.h>
  69. #include <asm/arch/mx6-ddr.h>
  70. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  71. .grp_addds = 0x00000030,
  72. .grp_ddrmode_ctl = 0x00020000,
  73. .grp_b0ds = 0x00000030,
  74. .grp_ctlds = 0x00000030,
  75. .grp_b1ds = 0x00000030,
  76. .grp_ddrpke = 0x00000000,
  77. .grp_ddrmode = 0x00020000,
  78. .grp_ddr_type = 0x000c0000,
  79. };
  80. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  81. .dram_dqm0 = 0x00000030,
  82. .dram_dqm1 = 0x00000030,
  83. .dram_ras = 0x00000030,
  84. .dram_cas = 0x00000030,
  85. .dram_odt0 = 0x00000030,
  86. .dram_odt1 = 0x00000030,
  87. .dram_sdba2 = 0x00000000,
  88. .dram_sdclk_0 = 0x00000030,
  89. .dram_sdqs0 = 0x00000030,
  90. .dram_sdqs1 = 0x00000030,
  91. .dram_reset = 0x00000030,
  92. };
  93. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  94. .p0_mpwldectrl0 = 0x00000000,
  95. .p0_mpdgctrl0 = 0x41570155,
  96. .p0_mprddlctl = 0x4040474A,
  97. .p0_mpwrdlctl = 0x40405550,
  98. };
  99. struct mx6_ddr_sysinfo ddr_sysinfo = {
  100. .dsize = 0,
  101. .cs_density = 20,
  102. .ncs = 1,
  103. .cs1_mirror = 0,
  104. .rtt_wr = 2,
  105. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  106. .walat = 0, /* Write additional latency */
  107. .ralat = 5, /* Read additional latency */
  108. .mif3_mode = 3, /* Command prediction working mode */
  109. .bi_on = 1, /* Bank interleaving enabled */
  110. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  111. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  112. .ddr_type = DDR_TYPE_DDR3,
  113. .refsel = 0, /* Refresh cycles at 64KHz */
  114. .refr = 1, /* 2 refresh commands per refresh cycle */
  115. };
  116. static struct mx6_ddr3_cfg mem_ddr = {
  117. .mem_speed = 800,
  118. .density = 4,
  119. .width = 16,
  120. .banks = 8,
  121. .rowaddr = 15,
  122. .coladdr = 10,
  123. .pagesz = 2,
  124. .trcd = 1375,
  125. .trcmin = 4875,
  126. .trasmin = 3500,
  127. };
  128. static void ccgr_init(void)
  129. {
  130. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  131. writel(0xFFFFFFFF, &ccm->CCGR0);
  132. writel(0xFFFFFFFF, &ccm->CCGR1);
  133. writel(0xFFFFFFFF, &ccm->CCGR2);
  134. writel(0xFFFFFFFF, &ccm->CCGR3);
  135. writel(0xFFFFFFFF, &ccm->CCGR4);
  136. writel(0xFFFFFFFF, &ccm->CCGR5);
  137. writel(0xFFFFFFFF, &ccm->CCGR6);
  138. writel(0xFFFFFFFF, &ccm->CCGR7);
  139. }
  140. static void spl_dram_init(void)
  141. {
  142. unsigned long ram_size;
  143. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  144. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  145. /*
  146. * Get actual RAM size, so we can adjust DDR row size for <512M
  147. * memories
  148. */
  149. ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
  150. if (ram_size < SZ_512M) {
  151. mem_ddr.rowaddr = 14;
  152. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  153. }
  154. }
  155. void litesom_init_f(void)
  156. {
  157. ccgr_init();
  158. /* setup AIPS and disable watchdog */
  159. arch_cpu_init();
  160. #ifdef CONFIG_BOARD_EARLY_INIT_F
  161. board_early_init_f();
  162. #endif
  163. /* setup GP timer */
  164. timer_init();
  165. /* UART clocks enabled and gd valid - init serial console */
  166. preloader_console_init();
  167. /* DDR initialization */
  168. spl_dram_init();
  169. }
  170. #endif