soc.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/mach-imx/hab.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/syscounter.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/armv8/mmu.h>
  20. #include <dm/uclass.h>
  21. #include <efi_loader.h>
  22. #include <env.h>
  23. #include <env_internal.h>
  24. #include <errno.h>
  25. #include <fdt_support.h>
  26. #include <fsl_wdog.h>
  27. #include <imx_sip.h>
  28. #include <linux/arm-smccc.h>
  29. #include <linux/bitops.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #if defined(CONFIG_IMX_HAB)
  32. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  33. .bank = 1,
  34. .word = 3,
  35. };
  36. #endif
  37. int timer_init(void)
  38. {
  39. #ifdef CONFIG_SPL_BUILD
  40. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  41. unsigned long freq = readl(&sctr->cntfid0);
  42. /* Update with accurate clock frequency */
  43. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  44. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  45. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  46. #endif
  47. gd->arch.tbl = 0;
  48. gd->arch.tbu = 0;
  49. return 0;
  50. }
  51. void enable_tzc380(void)
  52. {
  53. struct iomuxc_gpr_base_regs *gpr =
  54. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  55. /* Enable TZASC and lock setting */
  56. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  57. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  58. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  59. setbits_le32(&gpr->gpr[10], BIT(1));
  60. /*
  61. * set Region 0 attribute to allow secure and non-secure
  62. * read/write permission. Found some masters like usb dwc3
  63. * controllers can't work with secure memory.
  64. */
  65. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  66. }
  67. void set_wdog_reset(struct wdog_regs *wdog)
  68. {
  69. /*
  70. * Output WDOG_B signal to reset external pmic or POR_B decided by
  71. * the board design. Without external reset, the peripherals/DDR/
  72. * PMIC are not reset, that may cause system working abnormal.
  73. * WDZST bit is write-once only bit. Align this bit in kernel,
  74. * otherwise kernel code will have no chance to set this bit.
  75. */
  76. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  77. }
  78. static struct mm_region imx8m_mem_map[] = {
  79. {
  80. /* ROM */
  81. .virt = 0x0UL,
  82. .phys = 0x0UL,
  83. .size = 0x100000UL,
  84. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  85. PTE_BLOCK_OUTER_SHARE
  86. }, {
  87. /* CAAM */
  88. .virt = 0x100000UL,
  89. .phys = 0x100000UL,
  90. .size = 0x8000UL,
  91. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  92. PTE_BLOCK_NON_SHARE |
  93. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  94. }, {
  95. /* TCM */
  96. .virt = 0x7C0000UL,
  97. .phys = 0x7C0000UL,
  98. .size = 0x80000UL,
  99. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  100. PTE_BLOCK_NON_SHARE |
  101. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  102. }, {
  103. /* OCRAM */
  104. .virt = 0x900000UL,
  105. .phys = 0x900000UL,
  106. .size = 0x200000UL,
  107. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  108. PTE_BLOCK_OUTER_SHARE
  109. }, {
  110. /* AIPS */
  111. .virt = 0xB00000UL,
  112. .phys = 0xB00000UL,
  113. .size = 0x3f500000UL,
  114. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  115. PTE_BLOCK_NON_SHARE |
  116. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  117. }, {
  118. /* DRAM1 */
  119. .virt = 0x40000000UL,
  120. .phys = 0x40000000UL,
  121. .size = PHYS_SDRAM_SIZE,
  122. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  123. PTE_BLOCK_OUTER_SHARE
  124. #ifdef PHYS_SDRAM_2_SIZE
  125. }, {
  126. /* DRAM2 */
  127. .virt = 0x100000000UL,
  128. .phys = 0x100000000UL,
  129. .size = PHYS_SDRAM_2_SIZE,
  130. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  131. PTE_BLOCK_OUTER_SHARE
  132. #endif
  133. }, {
  134. /* empty entrie to split table entry 5 if needed when TEEs are used */
  135. 0,
  136. }, {
  137. /* List terminator */
  138. 0,
  139. }
  140. };
  141. struct mm_region *mem_map = imx8m_mem_map;
  142. void enable_caches(void)
  143. {
  144. /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
  145. if (rom_pointer[1]) {
  146. /*
  147. * TEE are loaded, So the ddr bank structures
  148. * have been modified update mmu table accordingly
  149. */
  150. int i = 0;
  151. /*
  152. * please make sure that entry initial value matches
  153. * imx8m_mem_map for DRAM1
  154. */
  155. int entry = 5;
  156. u64 attrs = imx8m_mem_map[entry].attrs;
  157. while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
  158. if (gd->bd->bi_dram[i].start == 0)
  159. break;
  160. imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
  161. imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
  162. imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
  163. imx8m_mem_map[entry].attrs = attrs;
  164. debug("Added memory mapping (%d): %llx %llx\n", entry,
  165. imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
  166. i++; entry++;
  167. }
  168. }
  169. icache_enable();
  170. dcache_enable();
  171. }
  172. __weak int board_phys_sdram_size(phys_size_t *size)
  173. {
  174. if (!size)
  175. return -EINVAL;
  176. *size = PHYS_SDRAM_SIZE;
  177. return 0;
  178. }
  179. int dram_init(void)
  180. {
  181. phys_size_t sdram_size;
  182. int ret;
  183. ret = board_phys_sdram_size(&sdram_size);
  184. if (ret)
  185. return ret;
  186. /* rom_pointer[1] contains the size of TEE occupies */
  187. if (rom_pointer[1])
  188. gd->ram_size = sdram_size - rom_pointer[1];
  189. else
  190. gd->ram_size = sdram_size;
  191. #ifdef PHYS_SDRAM_2_SIZE
  192. gd->ram_size += PHYS_SDRAM_2_SIZE;
  193. #endif
  194. return 0;
  195. }
  196. int dram_init_banksize(void)
  197. {
  198. int bank = 0;
  199. int ret;
  200. phys_size_t sdram_size;
  201. ret = board_phys_sdram_size(&sdram_size);
  202. if (ret)
  203. return ret;
  204. gd->bd->bi_dram[bank].start = PHYS_SDRAM;
  205. if (rom_pointer[1]) {
  206. phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
  207. phys_size_t optee_size = (size_t)rom_pointer[1];
  208. gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
  209. if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
  210. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  211. puts("CONFIG_NR_DRAM_BANKS is not enough\n");
  212. return -1;
  213. }
  214. gd->bd->bi_dram[bank].start = optee_start + optee_size;
  215. gd->bd->bi_dram[bank].size = PHYS_SDRAM +
  216. sdram_size - gd->bd->bi_dram[bank].start;
  217. }
  218. } else {
  219. gd->bd->bi_dram[bank].size = sdram_size;
  220. }
  221. #ifdef PHYS_SDRAM_2_SIZE
  222. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  223. puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
  224. return -1;
  225. }
  226. gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
  227. gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
  228. #endif
  229. return 0;
  230. }
  231. phys_size_t get_effective_memsize(void)
  232. {
  233. /* return the first bank as effective memory */
  234. if (rom_pointer[1])
  235. return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
  236. #ifdef PHYS_SDRAM_2_SIZE
  237. return gd->ram_size - PHYS_SDRAM_2_SIZE;
  238. #else
  239. return gd->ram_size;
  240. #endif
  241. }
  242. static u32 get_cpu_variant_type(u32 type)
  243. {
  244. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  245. struct fuse_bank *bank = &ocotp->bank[1];
  246. struct fuse_bank1_regs *fuse =
  247. (struct fuse_bank1_regs *)bank->fuse_regs;
  248. u32 value = readl(&fuse->tester4);
  249. if (type == MXC_CPU_IMX8MQ) {
  250. if ((value & 0x3) == 0x2)
  251. return MXC_CPU_IMX8MD;
  252. else if (value & 0x200000)
  253. return MXC_CPU_IMX8MQL;
  254. } else if (type == MXC_CPU_IMX8MM) {
  255. switch (value & 0x3) {
  256. case 2:
  257. if (value & 0x1c0000)
  258. return MXC_CPU_IMX8MMDL;
  259. else
  260. return MXC_CPU_IMX8MMD;
  261. case 3:
  262. if (value & 0x1c0000)
  263. return MXC_CPU_IMX8MMSL;
  264. else
  265. return MXC_CPU_IMX8MMS;
  266. default:
  267. if (value & 0x1c0000)
  268. return MXC_CPU_IMX8MML;
  269. break;
  270. }
  271. } else if (type == MXC_CPU_IMX8MN) {
  272. switch (value & 0x3) {
  273. case 2:
  274. if (value & 0x1000000)
  275. return MXC_CPU_IMX8MNDL;
  276. else
  277. return MXC_CPU_IMX8MND;
  278. case 3:
  279. if (value & 0x1000000)
  280. return MXC_CPU_IMX8MNSL;
  281. else
  282. return MXC_CPU_IMX8MNS;
  283. default:
  284. if (value & 0x1000000)
  285. return MXC_CPU_IMX8MNL;
  286. break;
  287. }
  288. } else if (type == MXC_CPU_IMX8MP) {
  289. u32 value0 = readl(&fuse->tester3);
  290. u32 flag = 0;
  291. if ((value0 & 0xc0000) == 0x80000)
  292. return MXC_CPU_IMX8MPD;
  293. /* vpu disabled */
  294. if ((value0 & 0x43000000) == 0x43000000)
  295. flag = 1;
  296. /* npu disabled*/
  297. if ((value & 0x8) == 0x8)
  298. flag |= (1 << 1);
  299. /* isp disabled */
  300. if ((value & 0x3) == 0x3)
  301. flag |= (1 << 2);
  302. switch (flag) {
  303. case 7:
  304. return MXC_CPU_IMX8MPL;
  305. case 6:
  306. return MXC_CPU_IMX8MP5;
  307. case 2:
  308. return MXC_CPU_IMX8MP6;
  309. case 1:
  310. return MXC_CPU_IMX8MP7;
  311. default:
  312. break;
  313. }
  314. }
  315. return type;
  316. }
  317. u32 get_cpu_rev(void)
  318. {
  319. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  320. u32 reg = readl(&ana_pll->digprog);
  321. u32 type = (reg >> 16) & 0xff;
  322. u32 major_low = (reg >> 8) & 0xff;
  323. u32 rom_version;
  324. reg &= 0xff;
  325. /* iMX8MP */
  326. if (major_low == 0x43) {
  327. type = get_cpu_variant_type(MXC_CPU_IMX8MP);
  328. } else if (major_low == 0x42) {
  329. /* iMX8MN */
  330. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  331. } else if (major_low == 0x41) {
  332. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  333. } else {
  334. if (reg == CHIP_REV_1_0) {
  335. /*
  336. * For B0 chip, the DIGPROG is not updated,
  337. * it is still TO1.0. we have to check ROM
  338. * version or OCOTP_READ_FUSE_DATA.
  339. * 0xff0055aa is magic number for B1.
  340. */
  341. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  342. reg = CHIP_REV_2_1;
  343. } else {
  344. rom_version =
  345. readl((void __iomem *)ROM_VERSION_A0);
  346. if (rom_version != CHIP_REV_1_0) {
  347. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  348. rom_version &= 0xff;
  349. if (rom_version == CHIP_REV_2_0)
  350. reg = CHIP_REV_2_0;
  351. }
  352. }
  353. }
  354. type = get_cpu_variant_type(type);
  355. }
  356. return (type << 12) | reg;
  357. }
  358. static void imx_set_wdog_powerdown(bool enable)
  359. {
  360. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  361. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  362. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  363. /* Write to the PDE (Power Down Enable) bit */
  364. writew(enable, &wdog1->wmcr);
  365. writew(enable, &wdog2->wmcr);
  366. writew(enable, &wdog3->wmcr);
  367. }
  368. int arch_cpu_init_dm(void)
  369. {
  370. struct udevice *dev;
  371. int ret;
  372. if (CONFIG_IS_ENABLED(CLK)) {
  373. ret = uclass_get_device_by_name(UCLASS_CLK,
  374. "clock-controller@30380000",
  375. &dev);
  376. if (ret < 0) {
  377. printf("Failed to find clock node. Check device tree\n");
  378. return ret;
  379. }
  380. }
  381. return 0;
  382. }
  383. int arch_cpu_init(void)
  384. {
  385. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  386. /*
  387. * ROM might disable clock for SCTR,
  388. * enable the clock before timer_init.
  389. */
  390. if (IS_ENABLED(CONFIG_SPL_BUILD))
  391. clock_enable(CCGR_SCTR, 1);
  392. /*
  393. * Init timer at very early state, because sscg pll setting
  394. * will use it
  395. */
  396. timer_init();
  397. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  398. clock_init();
  399. imx_set_wdog_powerdown(false);
  400. if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
  401. is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
  402. is_imx8mnsl() || is_imx8mpd()) {
  403. /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
  404. struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
  405. struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
  406. struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
  407. struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
  408. writel(0x1, &pgc_core2->pgcr);
  409. writel(0x1, &pgc_core3->pgcr);
  410. if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
  411. writel(0x1, &pgc_core1->pgcr);
  412. writel(0xE, &gpc->cpu_pgc_dn_trg);
  413. } else {
  414. writel(0xC, &gpc->cpu_pgc_dn_trg);
  415. }
  416. }
  417. }
  418. if (is_imx8mq()) {
  419. clock_enable(CCGR_OCOTP, 1);
  420. if (readl(&ocotp->ctrl) & 0x200)
  421. writel(0x200, &ocotp->ctrl_clr);
  422. }
  423. return 0;
  424. }
  425. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  426. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  427. enum boot_device get_boot_device(void)
  428. {
  429. volatile gd_t *pgd = gd;
  430. int ret;
  431. u32 boot;
  432. u16 boot_type;
  433. u8 boot_instance;
  434. enum boot_device boot_dev = SD1_BOOT;
  435. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  436. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  437. gd = pgd;
  438. if (ret != ROM_API_OKAY) {
  439. puts("ROMAPI: failure at query_boot_info\n");
  440. return -1;
  441. }
  442. boot_type = boot >> 16;
  443. boot_instance = (boot >> 8) & 0xff;
  444. switch (boot_type) {
  445. case BT_DEV_TYPE_SD:
  446. boot_dev = boot_instance + SD1_BOOT;
  447. break;
  448. case BT_DEV_TYPE_MMC:
  449. boot_dev = boot_instance + MMC1_BOOT;
  450. break;
  451. case BT_DEV_TYPE_NAND:
  452. boot_dev = NAND_BOOT;
  453. break;
  454. case BT_DEV_TYPE_FLEXSPINOR:
  455. boot_dev = QSPI_BOOT;
  456. break;
  457. case BT_DEV_TYPE_USB:
  458. boot_dev = USB_BOOT;
  459. break;
  460. default:
  461. break;
  462. }
  463. return boot_dev;
  464. }
  465. #endif
  466. bool is_usb_boot(void)
  467. {
  468. return get_boot_device() == USB_BOOT;
  469. }
  470. #ifdef CONFIG_OF_SYSTEM_SETUP
  471. bool check_fdt_new_path(void *blob)
  472. {
  473. const char *soc_path = "/soc@0";
  474. int nodeoff;
  475. nodeoff = fdt_path_offset(blob, soc_path);
  476. if (nodeoff < 0)
  477. return false;
  478. return true;
  479. }
  480. static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
  481. {
  482. int i = 0;
  483. int rc;
  484. int nodeoff;
  485. const char *status = "disabled";
  486. for (i = 0; i < size_array; i++) {
  487. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  488. if (nodeoff < 0)
  489. continue; /* Not found, skip it */
  490. printf("Found %s node\n", nodes_path[i]);
  491. add_status:
  492. rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
  493. if (rc) {
  494. if (rc == -FDT_ERR_NOSPACE) {
  495. rc = fdt_increase_size(blob, 512);
  496. if (!rc)
  497. goto add_status;
  498. }
  499. printf("Unable to update property %s:%s, err=%s\n",
  500. nodes_path[i], "status", fdt_strerror(rc));
  501. } else {
  502. printf("Modify %s:%s disabled\n",
  503. nodes_path[i], "status");
  504. }
  505. }
  506. return 0;
  507. }
  508. #ifdef CONFIG_IMX8MQ
  509. bool check_dcss_fused(void)
  510. {
  511. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  512. struct fuse_bank *bank = &ocotp->bank[1];
  513. struct fuse_bank1_regs *fuse =
  514. (struct fuse_bank1_regs *)bank->fuse_regs;
  515. u32 value = readl(&fuse->tester4);
  516. if (value & 0x4000000)
  517. return true;
  518. return false;
  519. }
  520. static int disable_mipi_dsi_nodes(void *blob)
  521. {
  522. static const char * const nodes_path[] = {
  523. "/mipi_dsi@30A00000",
  524. "/mipi_dsi_bridge@30A00000",
  525. "/dsi_phy@30A00300",
  526. "/soc@0/bus@30800000/mipi_dsi@30a00000",
  527. "/soc@0/bus@30800000/dphy@30a00300"
  528. };
  529. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  530. }
  531. static int disable_dcss_nodes(void *blob)
  532. {
  533. static const char * const nodes_path[] = {
  534. "/dcss@0x32e00000",
  535. "/dcss@32e00000",
  536. "/hdmi@32c00000",
  537. "/hdmi_cec@32c33800",
  538. "/hdmi_drm@32c00000",
  539. "/display-subsystem",
  540. "/sound-hdmi",
  541. "/sound-hdmi-arc",
  542. "/soc@0/bus@32c00000/display-controller@32e00000",
  543. "/soc@0/bus@32c00000/hdmi@32c00000",
  544. };
  545. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  546. }
  547. static int check_mipi_dsi_nodes(void *blob)
  548. {
  549. static const char * const lcdif_path[] = {
  550. "/lcdif@30320000",
  551. "/soc@0/bus@30000000/lcdif@30320000"
  552. };
  553. static const char * const mipi_dsi_path[] = {
  554. "/mipi_dsi@30A00000",
  555. "/soc@0/bus@30800000/mipi_dsi@30a00000"
  556. };
  557. static const char * const lcdif_ep_path[] = {
  558. "/lcdif@30320000/port@0/mipi-dsi-endpoint",
  559. "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint"
  560. };
  561. static const char * const mipi_dsi_ep_path[] = {
  562. "/mipi_dsi@30A00000/port@1/endpoint",
  563. "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint"
  564. };
  565. int lookup_node;
  566. int nodeoff;
  567. bool new_path = check_fdt_new_path(blob);
  568. int i = new_path ? 1 : 0;
  569. nodeoff = fdt_path_offset(blob, lcdif_path[i]);
  570. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
  571. /*
  572. * If can't find lcdif node or lcdif node is disabled,
  573. * then disable all mipi dsi, since they only can input
  574. * from DCSS
  575. */
  576. return disable_mipi_dsi_nodes(blob);
  577. }
  578. nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
  579. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
  580. return 0;
  581. nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
  582. if (nodeoff < 0) {
  583. /*
  584. * If can't find lcdif endpoint, then disable all mipi dsi,
  585. * since they only can input from DCSS
  586. */
  587. return disable_mipi_dsi_nodes(blob);
  588. }
  589. lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
  590. nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
  591. if (nodeoff > 0 && nodeoff == lookup_node)
  592. return 0;
  593. return disable_mipi_dsi_nodes(blob);
  594. }
  595. #endif
  596. int disable_vpu_nodes(void *blob)
  597. {
  598. static const char * const nodes_path_8mq[] = {
  599. "/vpu@38300000",
  600. "/soc@0/vpu@38300000"
  601. };
  602. static const char * const nodes_path_8mm[] = {
  603. "/vpu_g1@38300000",
  604. "/vpu_g2@38310000",
  605. "/vpu_h1@38320000"
  606. };
  607. static const char * const nodes_path_8mp[] = {
  608. "/vpu_g1@38300000",
  609. "/vpu_g2@38310000",
  610. "/vpu_vc8000e@38320000"
  611. };
  612. if (is_imx8mq())
  613. return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
  614. else if (is_imx8mm())
  615. return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
  616. else if (is_imx8mp())
  617. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  618. else
  619. return -EPERM;
  620. }
  621. int disable_gpu_nodes(void *blob)
  622. {
  623. static const char * const nodes_path_8mn[] = {
  624. "/gpu@38000000"
  625. };
  626. return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
  627. }
  628. int disable_npu_nodes(void *blob)
  629. {
  630. static const char * const nodes_path_8mp[] = {
  631. "/vipsi@38500000"
  632. };
  633. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  634. }
  635. int disable_isp_nodes(void *blob)
  636. {
  637. static const char * const nodes_path_8mp[] = {
  638. "/soc@0/bus@32c00000/camera/isp@32e10000",
  639. "/soc@0/bus@32c00000/camera/isp@32e20000"
  640. };
  641. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  642. }
  643. int disable_dsp_nodes(void *blob)
  644. {
  645. static const char * const nodes_path_8mp[] = {
  646. "/dsp@3b6e8000"
  647. };
  648. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  649. }
  650. static int disable_cpu_nodes(void *blob, u32 disabled_cores)
  651. {
  652. static const char * const nodes_path[] = {
  653. "/cpus/cpu@1",
  654. "/cpus/cpu@2",
  655. "/cpus/cpu@3",
  656. };
  657. u32 i = 0;
  658. int rc;
  659. int nodeoff;
  660. if (disabled_cores > 3)
  661. return -EINVAL;
  662. i = 3 - disabled_cores;
  663. for (; i < 3; i++) {
  664. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  665. if (nodeoff < 0)
  666. continue; /* Not found, skip it */
  667. debug("Found %s node\n", nodes_path[i]);
  668. rc = fdt_del_node(blob, nodeoff);
  669. if (rc < 0) {
  670. printf("Unable to delete node %s, err=%s\n",
  671. nodes_path[i], fdt_strerror(rc));
  672. } else {
  673. printf("Delete node %s\n", nodes_path[i]);
  674. }
  675. }
  676. return 0;
  677. }
  678. int ft_system_setup(void *blob, struct bd_info *bd)
  679. {
  680. #ifdef CONFIG_IMX8MQ
  681. int i = 0;
  682. int rc;
  683. int nodeoff;
  684. if (get_boot_device() == USB_BOOT) {
  685. disable_dcss_nodes(blob);
  686. bool new_path = check_fdt_new_path(blob);
  687. int v = new_path ? 1 : 0;
  688. static const char * const usb_dwc3_path[] = {
  689. "/usb@38100000/dwc3",
  690. "/soc@0/usb@38100000"
  691. };
  692. nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
  693. if (nodeoff >= 0) {
  694. const char *speed = "high-speed";
  695. printf("Found %s node\n", usb_dwc3_path[v]);
  696. usb_modify_speed:
  697. rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
  698. if (rc) {
  699. if (rc == -FDT_ERR_NOSPACE) {
  700. rc = fdt_increase_size(blob, 512);
  701. if (!rc)
  702. goto usb_modify_speed;
  703. }
  704. printf("Unable to set property %s:%s, err=%s\n",
  705. usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
  706. } else {
  707. printf("Modify %s:%s = %s\n",
  708. usb_dwc3_path[v], "maximum-speed", speed);
  709. }
  710. } else {
  711. printf("Can't found %s node\n", usb_dwc3_path[v]);
  712. }
  713. }
  714. /* Disable the CPU idle for A0 chip since the HW does not support it */
  715. if (is_soc_rev(CHIP_REV_1_0)) {
  716. static const char * const nodes_path[] = {
  717. "/cpus/cpu@0",
  718. "/cpus/cpu@1",
  719. "/cpus/cpu@2",
  720. "/cpus/cpu@3",
  721. };
  722. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  723. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  724. if (nodeoff < 0)
  725. continue; /* Not found, skip it */
  726. debug("Found %s node\n", nodes_path[i]);
  727. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  728. if (rc == -FDT_ERR_NOTFOUND)
  729. continue;
  730. if (rc) {
  731. printf("Unable to update property %s:%s, err=%s\n",
  732. nodes_path[i], "status", fdt_strerror(rc));
  733. return rc;
  734. }
  735. debug("Remove %s:%s\n", nodes_path[i],
  736. "cpu-idle-states");
  737. }
  738. }
  739. if (is_imx8mql()) {
  740. disable_vpu_nodes(blob);
  741. if (check_dcss_fused()) {
  742. printf("DCSS is fused\n");
  743. disable_dcss_nodes(blob);
  744. check_mipi_dsi_nodes(blob);
  745. }
  746. }
  747. if (is_imx8md())
  748. disable_cpu_nodes(blob, 2);
  749. #elif defined(CONFIG_IMX8MM)
  750. if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
  751. disable_vpu_nodes(blob);
  752. if (is_imx8mmd() || is_imx8mmdl())
  753. disable_cpu_nodes(blob, 2);
  754. else if (is_imx8mms() || is_imx8mmsl())
  755. disable_cpu_nodes(blob, 3);
  756. #elif defined(CONFIG_IMX8MN)
  757. if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
  758. disable_gpu_nodes(blob);
  759. if (is_imx8mnd() || is_imx8mndl())
  760. disable_cpu_nodes(blob, 2);
  761. else if (is_imx8mns() || is_imx8mnsl())
  762. disable_cpu_nodes(blob, 3);
  763. #elif defined(CONFIG_IMX8MP)
  764. if (is_imx8mpl() || is_imx8mp7())
  765. disable_vpu_nodes(blob);
  766. if (is_imx8mpl() || is_imx8mp6() || is_imx8mp5())
  767. disable_npu_nodes(blob);
  768. if (is_imx8mpl() || is_imx8mp5())
  769. disable_isp_nodes(blob);
  770. if (is_imx8mpl() || is_imx8mp7() || is_imx8mp6() || is_imx8mp5())
  771. disable_dsp_nodes(blob);
  772. if (is_imx8mpd())
  773. disable_cpu_nodes(blob, 2);
  774. #endif
  775. return 0;
  776. }
  777. #endif
  778. #if !CONFIG_IS_ENABLED(SYSRESET)
  779. void reset_cpu(ulong addr)
  780. {
  781. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  782. /* Clear WDA to trigger WDOG_B immediately */
  783. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  784. while (1) {
  785. /*
  786. * spin for .5 seconds before reset
  787. */
  788. }
  789. }
  790. #endif
  791. #if defined(CONFIG_ARCH_MISC_INIT)
  792. static void acquire_buildinfo(void)
  793. {
  794. u64 atf_commit = 0;
  795. struct arm_smccc_res res;
  796. /* Get ARM Trusted Firmware commit id */
  797. arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
  798. 0, 0 , 0, 0, 0, 0, &res);
  799. atf_commit = res.a0;
  800. if (atf_commit == 0xffffffff) {
  801. debug("ATF does not support build info\n");
  802. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  803. }
  804. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  805. }
  806. int arch_misc_init(void)
  807. {
  808. acquire_buildinfo();
  809. return 0;
  810. }
  811. #endif
  812. void imx_tmu_arch_init(void *reg_base)
  813. {
  814. if (is_imx8mm() || is_imx8mn()) {
  815. /* Load TCALIV and TASR from fuses */
  816. struct ocotp_regs *ocotp =
  817. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  818. struct fuse_bank *bank = &ocotp->bank[3];
  819. struct fuse_bank3_regs *fuse =
  820. (struct fuse_bank3_regs *)bank->fuse_regs;
  821. u32 tca_rt, tca_hr, tca_en;
  822. u32 buf_vref, buf_slope;
  823. tca_rt = fuse->ana0 & 0xFF;
  824. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  825. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  826. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  827. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  828. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  829. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  830. (ulong)reg_base + 0x30);
  831. }
  832. #ifdef CONFIG_IMX8MP
  833. /* Load TCALIV0/1/m40 and TRIM from fuses */
  834. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  835. struct fuse_bank *bank = &ocotp->bank[38];
  836. struct fuse_bank38_regs *fuse =
  837. (struct fuse_bank38_regs *)bank->fuse_regs;
  838. struct fuse_bank *bank2 = &ocotp->bank[39];
  839. struct fuse_bank39_regs *fuse2 =
  840. (struct fuse_bank39_regs *)bank2->fuse_regs;
  841. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  842. u32 reg;
  843. u32 tca40[2], tca25[2], tca105[2];
  844. /* For blank sample */
  845. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  846. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  847. /* Use a default 25C binary codes */
  848. tca25[0] = 1596;
  849. tca25[1] = 1596;
  850. writel(tca25[0], (ulong)reg_base + 0x30);
  851. writel(tca25[1], (ulong)reg_base + 0x34);
  852. return;
  853. }
  854. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  855. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  856. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  857. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  858. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  859. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  860. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  861. writel(reg, (ulong)reg_base + 0x3c);
  862. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  863. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  864. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  865. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  866. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  867. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  868. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  869. /* use 25c for 1p calibration */
  870. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  871. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  872. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  873. #endif
  874. }
  875. #if defined(CONFIG_SPL_BUILD)
  876. #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
  877. bool serror_need_skip = true;
  878. void do_error(struct pt_regs *pt_regs, unsigned int esr)
  879. {
  880. /*
  881. * If stack is still in ROM reserved OCRAM not switch to SPL,
  882. * it is the ROM SError
  883. */
  884. ulong sp;
  885. asm volatile("mov %0, sp" : "=r"(sp) : );
  886. if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
  887. /* Check for ERR050342, imx8mq HDCP enabled parts */
  888. if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
  889. serror_need_skip = false;
  890. return; /* Do nothing skip the SError in ROM */
  891. }
  892. /* Check for ERR050350, field return mode for imx8mq, mm and mn */
  893. if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
  894. serror_need_skip = false;
  895. return; /* Do nothing skip the SError in ROM */
  896. }
  897. }
  898. efi_restore_gd();
  899. printf("\"Error\" handler, esr 0x%08x\n", esr);
  900. show_regs(pt_regs);
  901. panic("Resetting CPU ...\n");
  902. }
  903. #endif
  904. #endif
  905. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  906. enum env_location env_get_location(enum env_operation op, int prio)
  907. {
  908. enum boot_device dev = get_boot_device();
  909. enum env_location env_loc = ENVL_UNKNOWN;
  910. if (prio)
  911. return env_loc;
  912. switch (dev) {
  913. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  914. case QSPI_BOOT:
  915. env_loc = ENVL_SPI_FLASH;
  916. break;
  917. #endif
  918. #ifdef CONFIG_ENV_IS_IN_NAND
  919. case NAND_BOOT:
  920. env_loc = ENVL_NAND;
  921. break;
  922. #endif
  923. #ifdef CONFIG_ENV_IS_IN_MMC
  924. case SD1_BOOT:
  925. case SD2_BOOT:
  926. case SD3_BOOT:
  927. case MMC1_BOOT:
  928. case MMC2_BOOT:
  929. case MMC3_BOOT:
  930. env_loc = ENVL_MMC;
  931. break;
  932. #endif
  933. default:
  934. #if defined(CONFIG_ENV_IS_NOWHERE)
  935. env_loc = ENVL_NOWHERE;
  936. #endif
  937. break;
  938. }
  939. return env_loc;
  940. }
  941. #ifndef ENV_IS_EMBEDDED
  942. long long env_get_offset(long long defautl_offset)
  943. {
  944. enum boot_device dev = get_boot_device();
  945. switch (dev) {
  946. case NAND_BOOT:
  947. return (60 << 20); /* 60MB offset for NAND */
  948. default:
  949. break;
  950. }
  951. return defautl_offset;
  952. }
  953. #endif
  954. #endif