clock_slice.c 66 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/io.h>
  11. #include <errno.h>
  12. static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
  13. #ifdef CONFIG_IMX8MQ
  14. static struct clk_root_map root_array[] = {
  15. {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
  16. {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  17. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  18. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  19. },
  20. {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
  21. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  22. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  23. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  24. },
  25. {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
  26. {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  27. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  28. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
  29. },
  30. {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
  31. {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  32. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  33. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  34. },
  35. {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
  36. {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  37. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  38. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  39. },
  40. {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
  41. {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  42. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
  43. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  44. },
  45. {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
  46. {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  47. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  48. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  49. },
  50. {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
  51. {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  52. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  53. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  54. },
  55. {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
  56. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
  57. AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  58. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
  59. },
  60. {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
  61. {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  62. SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  63. EXT_CLK_1, EXT_CLK_4}
  64. },
  65. {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
  66. {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  67. SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  68. EXT_CLK_1, EXT_CLK_3}
  69. },
  70. {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
  71. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
  72. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  73. EXT_CLK_2, EXT_CLK_3}
  74. },
  75. {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
  76. {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  77. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  78. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  79. },
  80. {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
  81. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  82. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  83. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  84. },
  85. {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
  86. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  87. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  88. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  89. },
  90. {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
  91. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  92. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  93. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  94. },
  95. {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
  96. {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
  97. SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
  98. SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  99. },
  100. {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
  101. {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
  102. SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
  103. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  104. },
  105. {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
  106. {}
  107. },
  108. {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
  109. {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  110. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
  111. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  112. },
  113. {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
  114. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
  115. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  116. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
  117. },
  118. {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
  119. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
  120. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
  121. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
  122. },
  123. {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
  124. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  125. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  126. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  127. },
  128. {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
  129. {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  130. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
  131. SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  132. },
  133. {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
  134. {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  135. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
  136. SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  137. },
  138. {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
  139. {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  140. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
  141. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
  142. },
  143. {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
  144. {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  145. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
  146. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
  147. },
  148. {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
  149. {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  150. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  151. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
  152. },
  153. {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
  154. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
  155. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  156. SYSTEM_PLL1_400M_CLK}
  157. },
  158. {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
  159. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
  160. SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  161. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
  162. },
  163. {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
  164. {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  165. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  166. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  167. },
  168. {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
  169. {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  170. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  171. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  172. },
  173. {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
  174. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  175. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  176. OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
  177. },
  178. {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
  179. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  180. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  181. OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
  182. },
  183. {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
  184. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  185. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  186. OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
  187. },
  188. {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
  189. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  190. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  191. OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
  192. },
  193. {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
  194. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  195. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  196. OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
  197. },
  198. {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
  199. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  200. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  201. OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
  202. },
  203. {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
  204. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  205. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  206. OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
  207. },
  208. {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
  209. {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  210. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  211. OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
  212. },
  213. {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
  214. {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
  215. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  216. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
  217. },
  218. {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
  219. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
  220. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  221. VIDEO_PLL_CLK}
  222. },
  223. {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
  224. {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
  225. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
  226. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  227. },
  228. {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
  229. {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
  230. SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
  231. SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
  232. },
  233. {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
  234. {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  235. SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  236. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  237. },
  238. {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
  239. {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  240. SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  241. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  242. },
  243. {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
  244. {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  245. SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  246. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  247. },
  248. {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
  249. {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  250. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  251. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  252. },
  253. {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
  254. {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  255. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  256. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  257. },
  258. {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
  259. {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  260. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  261. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  262. },
  263. {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
  264. {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  265. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  266. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  267. },
  268. {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
  269. {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  270. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  271. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  272. },
  273. {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
  274. {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  275. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  276. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  277. },
  278. {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
  279. {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  280. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  281. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  282. },
  283. {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
  284. {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  285. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  286. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  287. },
  288. {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
  289. {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  290. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  291. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  292. },
  293. {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
  294. {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  295. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  296. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  297. },
  298. {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
  299. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  300. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
  301. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  302. },
  303. {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
  304. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  305. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  306. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  307. },
  308. {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
  309. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  310. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  311. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  312. },
  313. {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
  314. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  315. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  316. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  317. },
  318. {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
  319. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  320. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  321. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  322. },
  323. {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
  324. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  325. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  326. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  327. },
  328. {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
  329. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  330. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  331. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  332. },
  333. {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
  334. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  335. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  336. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  337. },
  338. {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
  339. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  340. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  341. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  342. },
  343. {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
  344. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  345. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  346. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  347. },
  348. {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
  349. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  350. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  351. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  352. },
  353. {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
  354. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  355. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  356. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  357. },
  358. {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
  359. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  360. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  361. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  362. },
  363. {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
  364. {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  365. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  366. SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
  367. },
  368. {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
  369. {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  370. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  371. SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
  372. },
  373. {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
  374. {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
  375. SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
  376. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
  377. },
  378. {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
  379. {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
  380. SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
  381. SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
  382. },
  383. {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
  384. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
  385. SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
  386. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
  387. },
  388. {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
  389. {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  390. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  391. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  392. },
  393. {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
  394. {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  395. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  396. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  397. },
  398. {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
  399. {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
  400. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  401. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  402. },
  403. {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
  404. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  405. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  406. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  407. },
  408. {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
  409. {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  410. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  411. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  412. },
  413. {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
  414. {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  415. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  416. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  417. },
  418. {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
  419. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  420. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  421. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  422. },
  423. {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
  424. {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  425. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  426. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  427. },
  428. {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
  429. {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  430. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  431. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  432. },
  433. {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
  434. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  435. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  436. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  437. },
  438. {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
  439. {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  440. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  441. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
  442. },
  443. {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
  444. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
  445. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
  446. EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
  447. },
  448. {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
  449. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
  450. SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
  451. SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
  452. },
  453. {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
  454. {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  455. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  456. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  457. },
  458. {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
  459. {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  460. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  461. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
  462. },
  463. {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
  464. {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
  465. VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  466. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  467. },
  468. {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
  469. {DRAM_PLL1_CLK}
  470. },
  471. {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
  472. {ARM_A53_ALT_CLK, ARM_PLL_CLK}
  473. },
  474. };
  475. #elif defined(CONFIG_IMX8MM)
  476. static struct clk_root_map root_array[] = {
  477. {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
  478. {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  479. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  480. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  481. },
  482. {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
  483. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  484. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  485. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  486. },
  487. {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
  488. {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  489. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  490. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
  491. },
  492. {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
  493. {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  494. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  495. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  496. },
  497. {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
  498. {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  499. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  500. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  501. },
  502. {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
  503. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  504. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
  505. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  506. },
  507. {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
  508. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  509. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  510. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  511. },
  512. {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
  513. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  514. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  515. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  516. },
  517. {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
  518. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
  519. AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  520. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
  521. },
  522. {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
  523. {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  524. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
  525. EXT_CLK_1, EXT_CLK_4}
  526. },
  527. {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
  528. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  529. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
  530. EXT_CLK_1, EXT_CLK_3}
  531. },
  532. {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
  533. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
  534. SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  535. EXT_CLK_2, EXT_CLK_3}
  536. },
  537. {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
  538. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  539. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  540. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  541. },
  542. {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
  543. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  544. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  545. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  546. },
  547. {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
  548. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  549. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  550. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  551. },
  552. {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
  553. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  554. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  555. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  556. },
  557. {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
  558. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
  559. SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
  560. SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  561. },
  562. {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
  563. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
  564. SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
  565. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  566. },
  567. {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
  568. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  569. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
  570. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  571. },
  572. {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
  573. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  574. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  575. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  576. },
  577. {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
  578. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
  579. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
  580. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
  581. },
  582. {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
  583. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  584. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  585. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  586. },
  587. {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
  588. {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  589. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
  590. SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  591. },
  592. {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
  593. {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  594. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
  595. SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  596. },
  597. {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
  598. {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
  599. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
  600. VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
  601. },
  602. {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
  603. {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
  604. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
  605. VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
  606. },
  607. {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
  608. {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  609. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  610. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
  611. },
  612. {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
  613. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
  614. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  615. SYSTEM_PLL1_400M_CLK}
  616. },
  617. {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
  618. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
  619. SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  620. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
  621. },
  622. {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
  623. {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  624. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  625. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  626. },
  627. {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
  628. {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  629. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  630. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  631. },
  632. {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
  633. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  634. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  635. OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
  636. },
  637. {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
  638. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  639. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  640. OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
  641. },
  642. {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
  643. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  644. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  645. OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
  646. },
  647. {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
  648. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  649. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  650. OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
  651. },
  652. {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
  653. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  654. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  655. OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
  656. },
  657. {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
  658. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  659. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  660. OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
  661. },
  662. {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
  663. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  664. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  665. OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
  666. },
  667. {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
  668. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  669. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  670. OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
  671. },
  672. {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
  673. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
  674. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  675. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
  676. },
  677. {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
  678. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
  679. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  680. VIDEO_PLL_CLK}
  681. },
  682. {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
  683. {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
  684. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
  685. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  686. },
  687. {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
  688. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
  689. SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
  690. SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
  691. },
  692. {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
  693. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
  694. SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  695. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  696. },
  697. {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
  698. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  699. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  700. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  701. },
  702. {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
  703. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  704. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  705. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  706. },
  707. {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
  708. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  709. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  710. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  711. },
  712. {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
  713. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  714. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  715. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  716. },
  717. {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
  718. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  719. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  720. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  721. },
  722. {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
  723. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  724. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  725. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  726. },
  727. {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
  728. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  729. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  730. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  731. },
  732. {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
  733. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  734. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  735. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  736. },
  737. {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
  738. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  739. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  740. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  741. },
  742. {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
  743. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  744. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  745. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  746. },
  747. {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
  748. {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  749. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  750. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  751. },
  752. {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
  753. {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  754. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  755. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  756. },
  757. {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
  758. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  759. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
  760. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  761. },
  762. {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
  763. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  764. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  765. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  766. },
  767. {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
  768. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  769. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  770. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  771. },
  772. {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
  773. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  774. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  775. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  776. },
  777. {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
  778. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  779. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  780. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  781. },
  782. {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
  783. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  784. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
  785. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  786. },
  787. {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
  788. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  789. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
  790. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  791. },
  792. {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
  793. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  794. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  795. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  796. },
  797. {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
  798. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  799. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  800. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  801. },
  802. {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
  803. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  804. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  805. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  806. },
  807. {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
  808. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  809. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  810. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  811. },
  812. {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
  813. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  814. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  815. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  816. },
  817. {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
  818. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  819. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  820. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  821. },
  822. {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
  823. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  824. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  825. SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
  826. },
  827. {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
  828. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  829. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  830. SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
  831. },
  832. {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
  833. {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
  834. SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
  835. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
  836. },
  837. {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
  838. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
  839. SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
  840. SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
  841. },
  842. {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
  843. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
  844. SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
  845. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
  846. },
  847. {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
  848. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  849. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  850. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  851. },
  852. {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
  853. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  854. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  855. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  856. },
  857. {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
  858. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
  859. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  860. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  861. },
  862. {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
  863. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  864. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  865. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  866. },
  867. {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
  868. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  869. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  870. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  871. },
  872. {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
  873. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
  874. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  875. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  876. },
  877. {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
  878. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  879. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  880. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  881. },
  882. {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
  883. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  884. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  885. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  886. },
  887. {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
  888. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
  889. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  890. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  891. },
  892. {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
  893. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  894. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  895. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  896. },
  897. {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
  898. {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  899. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  900. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
  901. },
  902. {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
  903. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
  904. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
  905. EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
  906. },
  907. {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
  908. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
  909. SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
  910. SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
  911. },
  912. {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
  913. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  914. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  915. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  916. },
  917. {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
  918. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
  919. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  920. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
  921. },
  922. {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
  923. {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  924. SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
  925. SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  926. },
  927. {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
  928. {DRAM_PLL1_CLK}
  929. },
  930. {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
  931. {ARM_A53_ALT_CLK, ARM_PLL_CLK}
  932. },
  933. };
  934. #elif defined(CONFIG_IMX8MN)
  935. static struct clk_root_map root_array[] = {
  936. {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
  937. {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  938. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  939. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  940. },
  941. {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
  942. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  943. VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  944. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  945. },
  946. {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
  947. {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  948. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  949. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  950. },
  951. {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
  952. {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  953. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  954. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  955. },
  956. {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
  957. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  958. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
  959. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  960. },
  961. {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
  962. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  963. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  964. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  965. },
  966. {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
  967. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  968. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  969. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  970. },
  971. {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
  972. {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  973. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
  974. EXT_CLK_1, EXT_CLK_4}
  975. },
  976. {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
  977. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  978. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
  979. EXT_CLK_1, EXT_CLK_3}
  980. },
  981. {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
  982. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  983. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  984. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  985. },
  986. {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
  987. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  988. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  989. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  990. },
  991. {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
  992. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  993. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  994. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  995. },
  996. {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
  997. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  998. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  999. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1000. },
  1001. {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
  1002. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
  1003. SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
  1004. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  1005. },
  1006. {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
  1007. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  1008. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
  1009. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  1010. },
  1011. {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
  1012. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
  1013. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
  1014. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
  1015. },
  1016. {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
  1017. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1018. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1019. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1020. },
  1021. {DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
  1022. {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  1023. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  1024. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  1025. },
  1026. {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
  1027. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  1028. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  1029. OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
  1030. },
  1031. {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
  1032. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  1033. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  1034. OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
  1035. },
  1036. {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
  1037. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  1038. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  1039. OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
  1040. },
  1041. {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
  1042. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  1043. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  1044. OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
  1045. },
  1046. {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
  1047. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  1048. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  1049. OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
  1050. },
  1051. {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
  1052. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
  1053. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1054. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
  1055. },
  1056. {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
  1057. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
  1058. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  1059. VIDEO_PLL_CLK}
  1060. },
  1061. {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
  1062. {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
  1063. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
  1064. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1065. },
  1066. {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
  1067. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
  1068. SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
  1069. SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
  1070. },
  1071. {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
  1072. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
  1073. SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  1074. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  1075. },
  1076. {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
  1077. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  1078. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  1079. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  1080. },
  1081. {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
  1082. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  1083. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  1084. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  1085. },
  1086. {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
  1087. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1088. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1089. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1090. },
  1091. {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
  1092. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1093. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1094. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1095. },
  1096. {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
  1097. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1098. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1099. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1100. },
  1101. {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
  1102. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1103. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1104. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1105. },
  1106. {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
  1107. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1108. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1109. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  1110. },
  1111. {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
  1112. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1113. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1114. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1115. },
  1116. {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
  1117. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1118. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1119. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  1120. },
  1121. {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
  1122. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1123. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1124. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1125. },
  1126. {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
  1127. {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  1128. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  1129. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1130. },
  1131. {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
  1132. {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  1133. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  1134. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1135. },
  1136. {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
  1137. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1138. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
  1139. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  1140. },
  1141. {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
  1142. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1143. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1144. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1145. },
  1146. {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
  1147. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1148. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1149. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1150. },
  1151. {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
  1152. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1153. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  1154. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1155. },
  1156. {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
  1157. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1158. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  1159. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1160. },
  1161. {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
  1162. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1163. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
  1164. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1165. },
  1166. {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
  1167. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1168. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
  1169. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1170. },
  1171. {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
  1172. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1173. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1174. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  1175. },
  1176. {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
  1177. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1178. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1179. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  1180. },
  1181. {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
  1182. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1183. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1184. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  1185. },
  1186. {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
  1187. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1188. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1189. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  1190. },
  1191. {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
  1192. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1193. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1194. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  1195. },
  1196. {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
  1197. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1198. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1199. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  1200. },
  1201. {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
  1202. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  1203. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  1204. SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
  1205. },
  1206. {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
  1207. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  1208. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  1209. SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
  1210. },
  1211. {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
  1212. {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
  1213. SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
  1214. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
  1215. },
  1216. {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
  1217. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
  1218. SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
  1219. SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
  1220. },
  1221. {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
  1222. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
  1223. SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
  1224. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
  1225. },
  1226. {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
  1227. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  1228. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1229. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1230. },
  1231. {DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
  1232. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  1233. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1234. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1235. },
  1236. {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
  1237. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
  1238. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1239. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1240. },
  1241. {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
  1242. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  1243. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  1244. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  1245. },
  1246. {DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58,
  1247. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  1248. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1249. SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1250. },
  1251. {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
  1252. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
  1253. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1254. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1255. },
  1256. {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
  1257. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
  1258. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1259. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1260. },
  1261. {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
  1262. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  1263. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1264. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  1265. },
  1266. {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
  1267. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1268. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1269. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1270. },
  1271. {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
  1272. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
  1273. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1274. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
  1275. },
  1276. {SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70,
  1277. {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  1278. VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  1279. OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
  1280. },
  1281. {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
  1282. {DRAM_PLL1_CLK}
  1283. },
  1284. {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
  1285. {ARM_A53_ALT_CLK, ARM_PLL_CLK}
  1286. },
  1287. };
  1288. #elif defined(CONFIG_IMX8MP)
  1289. static struct clk_root_map root_array[] = {
  1290. {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
  1291. {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  1292. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  1293. SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  1294. },
  1295. {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
  1296. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  1297. VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  1298. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  1299. },
  1300. {ML_CLK_ROOT, CORE_CLOCK_SLICE, 2,
  1301. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  1302. VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  1303. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  1304. },
  1305. {HSIO_AXI_CLK_ROOT, CORE_CLOCK_SLICE, 7,
  1306. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  1307. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, EXT_CLK_2,
  1308. EXT_CLK_4, AUDIO_PLL2_CLK}
  1309. },
  1310. {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
  1311. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  1312. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK,
  1313. VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  1314. },
  1315. {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
  1316. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  1317. SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK,
  1318. VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  1319. },
  1320. {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
  1321. {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  1322. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  1323. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  1324. },
  1325. {MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
  1326. {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  1327. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
  1328. AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
  1329. },
  1330. {MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
  1331. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  1332. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
  1333. AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
  1334. },
  1335. {HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6,
  1336. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  1337. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
  1338. AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
  1339. },
  1340. {HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7,
  1341. {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  1342. SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
  1343. AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
  1344. },
  1345. {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
  1346. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  1347. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  1348. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1349. },
  1350. {NOC_IO_CLK_ROOT, BUS_CLOCK_SLICE, 11,
  1351. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  1352. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  1353. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1354. },
  1355. {ML_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 12,
  1356. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  1357. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  1358. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1359. },
  1360. {ML_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 13,
  1361. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  1362. SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  1363. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1364. },
  1365. {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
  1366. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
  1367. SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
  1368. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  1369. },
  1370. {MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3,
  1371. {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  1372. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  1373. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  1374. },
  1375. {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
  1376. {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
  1377. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
  1378. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
  1379. },
  1380. {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
  1381. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1382. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1383. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1384. },
  1385. {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
  1386. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1387. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  1388. SYSTEM_PLL1_133M_CLK}
  1389. },
  1390. {I2C6_CLK_ROOT, IP_CLOCK_SLICE, 10,
  1391. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1392. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  1393. SYSTEM_PLL1_133M_CLK}
  1394. },
  1395. {ENET_QOS_CLK_ROOT, IP_CLOCK_SLICE, 17,
  1396. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
  1397. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1398. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
  1399. },
  1400. {ENET_QOS_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 18,
  1401. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
  1402. EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
  1403. },
  1404. {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
  1405. {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
  1406. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1407. AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
  1408. },
  1409. {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
  1410. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
  1411. EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
  1412. },
  1413. {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
  1414. {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
  1415. SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
  1416. VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  1417. },
  1418. {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
  1419. {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
  1420. SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
  1421. SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
  1422. },
  1423. {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
  1424. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
  1425. SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  1426. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  1427. },
  1428. {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
  1429. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  1430. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  1431. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  1432. },
  1433. {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
  1434. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  1435. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  1436. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  1437. },
  1438. {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
  1439. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1440. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1441. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1442. },
  1443. {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
  1444. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1445. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1446. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1447. },
  1448. {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
  1449. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1450. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1451. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1452. },
  1453. {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
  1454. {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  1455. SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  1456. AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  1457. },
  1458. {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
  1459. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1460. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1461. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  1462. },
  1463. {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
  1464. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1465. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1466. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1467. },
  1468. {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
  1469. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1470. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1471. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  1472. },
  1473. {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
  1474. {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  1475. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  1476. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1477. },
  1478. {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
  1479. {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  1480. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  1481. EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  1482. },
  1483. {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
  1484. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1485. SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
  1486. EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  1487. },
  1488. {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
  1489. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1490. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1491. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1492. },
  1493. {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
  1494. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1495. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1496. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1497. },
  1498. {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
  1499. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1500. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  1501. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1502. },
  1503. {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
  1504. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1505. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  1506. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1507. },
  1508. {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
  1509. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1510. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
  1511. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1512. },
  1513. {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
  1514. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  1515. SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
  1516. SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  1517. },
  1518. {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
  1519. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1520. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1521. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  1522. },
  1523. {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
  1524. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1525. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1526. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  1527. },
  1528. {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
  1529. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1530. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1531. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  1532. },
  1533. {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
  1534. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1535. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1536. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  1537. },
  1538. {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
  1539. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1540. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1541. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  1542. },
  1543. {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
  1544. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  1545. SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  1546. SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  1547. },
  1548. {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
  1549. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  1550. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  1551. SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
  1552. },
  1553. {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
  1554. {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  1555. VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  1556. SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
  1557. },
  1558. {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
  1559. {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
  1560. SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
  1561. SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
  1562. },
  1563. {HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56,
  1564. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
  1565. SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK,
  1566. SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  1567. },
  1568. {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
  1569. {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  1570. SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
  1571. SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
  1572. },
  1573. {MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
  1574. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
  1575. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1576. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1577. },
  1578. {MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60,
  1579. {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  1580. AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  1581. SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  1582. },
  1583. {MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62,
  1584. {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
  1585. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1586. EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  1587. },
  1588. {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63,
  1589. {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  1590. SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  1591. SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  1592. },
  1593. {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
  1594. {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  1595. SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  1596. SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  1597. },
  1598. {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
  1599. {DRAM_PLL1_CLK}
  1600. },
  1601. {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
  1602. {ARM_A53_ALT_CLK, ARM_PLL_CLK}
  1603. },
  1604. };
  1605. #endif
  1606. static int select(enum clk_root_index clock_id)
  1607. {
  1608. int i, size;
  1609. struct clk_root_map *p = root_array;
  1610. size = ARRAY_SIZE(root_array);
  1611. for (i = 0; i < size; i++, p++) {
  1612. if (clock_id == p->entry)
  1613. return i;
  1614. }
  1615. return -EINVAL;
  1616. }
  1617. static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
  1618. u32 slice_index)
  1619. {
  1620. void __iomem *clk_root_target;
  1621. switch (slice_type) {
  1622. case CORE_CLOCK_SLICE:
  1623. clk_root_target =
  1624. (void __iomem *)&ccm_reg->core_root[slice_index];
  1625. break;
  1626. case BUS_CLOCK_SLICE:
  1627. clk_root_target =
  1628. (void __iomem *)&ccm_reg->bus_root[slice_index];
  1629. break;
  1630. case IP_CLOCK_SLICE:
  1631. clk_root_target =
  1632. (void __iomem *)&ccm_reg->ip_root[slice_index];
  1633. break;
  1634. case AHB_CLOCK_SLICE:
  1635. clk_root_target =
  1636. (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
  1637. break;
  1638. case IPG_CLOCK_SLICE:
  1639. clk_root_target =
  1640. (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
  1641. break;
  1642. case CORE_SEL_CLOCK_SLICE:
  1643. clk_root_target = (void __iomem *)&ccm_reg->core_sel;
  1644. break;
  1645. case DRAM_SEL_CLOCK_SLICE:
  1646. clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
  1647. break;
  1648. default:
  1649. return NULL;
  1650. }
  1651. return clk_root_target;
  1652. }
  1653. int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
  1654. {
  1655. int root_entry;
  1656. struct clk_root_map *p;
  1657. void __iomem *clk_root_target;
  1658. if (clock_id >= CLK_ROOT_MAX)
  1659. return -EINVAL;
  1660. root_entry = select(clock_id);
  1661. if (root_entry < 0)
  1662. return -EINVAL;
  1663. p = &root_array[root_entry];
  1664. clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
  1665. if (!clk_root_target)
  1666. return -EINVAL;
  1667. *val = readl(clk_root_target);
  1668. return 0;
  1669. }
  1670. int clock_set_target_val(enum clk_root_index clock_id, u32 val)
  1671. {
  1672. int root_entry;
  1673. struct clk_root_map *p;
  1674. void __iomem *clk_root_target;
  1675. if (clock_id >= CLK_ROOT_MAX)
  1676. return -EINVAL;
  1677. root_entry = select(clock_id);
  1678. if (root_entry < 0)
  1679. return -EINVAL;
  1680. p = &root_array[root_entry];
  1681. clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
  1682. if (!clk_root_target)
  1683. return -EINVAL;
  1684. writel(val, clk_root_target);
  1685. return 0;
  1686. }
  1687. int clock_root_enabled(enum clk_root_index clock_id)
  1688. {
  1689. void __iomem *clk_root_target;
  1690. u32 slice_index, slice_type;
  1691. u32 val;
  1692. int root_entry;
  1693. if (clock_id >= CLK_ROOT_MAX)
  1694. return -EINVAL;
  1695. root_entry = select(clock_id);
  1696. if (root_entry < 0)
  1697. return -EINVAL;
  1698. slice_type = root_array[root_entry].slice_type;
  1699. slice_index = root_array[root_entry].slice_index;
  1700. if ((slice_type == IPG_CLOCK_SLICE) ||
  1701. (slice_type == DRAM_SEL_CLOCK_SLICE) ||
  1702. (slice_type == CORE_SEL_CLOCK_SLICE)) {
  1703. /*
  1704. * Not supported, from CCM doc
  1705. * TODO
  1706. */
  1707. return 0;
  1708. }
  1709. clk_root_target = get_clk_root_target(slice_type, slice_index);
  1710. if (!clk_root_target)
  1711. return -EINVAL;
  1712. val = readl(clk_root_target);
  1713. return (val & CLK_ROOT_ON) ? 1 : 0;
  1714. }
  1715. /* CCGR CLK gate operation */
  1716. int clock_enable(enum clk_ccgr_index index, bool enable)
  1717. {
  1718. void __iomem *ccgr;
  1719. if (index >= CCGR_MAX)
  1720. return -EINVAL;
  1721. if (enable)
  1722. ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
  1723. else
  1724. ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
  1725. writel(CCGR_CLK_ON_MASK, ccgr);
  1726. return 0;
  1727. }
  1728. int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
  1729. {
  1730. u32 val;
  1731. int root_entry;
  1732. struct clk_root_map *p;
  1733. void __iomem *clk_root_target;
  1734. if (clock_id >= CLK_ROOT_MAX)
  1735. return -EINVAL;
  1736. root_entry = select(clock_id);
  1737. if (root_entry < 0)
  1738. return -EINVAL;
  1739. p = &root_array[root_entry];
  1740. if ((p->slice_type == CORE_CLOCK_SLICE) ||
  1741. (p->slice_type == IPG_CLOCK_SLICE) ||
  1742. (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
  1743. (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
  1744. *pre_div = 0;
  1745. return 0;
  1746. }
  1747. clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
  1748. if (!clk_root_target)
  1749. return -EINVAL;
  1750. val = readl(clk_root_target);
  1751. val &= CLK_ROOT_PRE_DIV_MASK;
  1752. val >>= CLK_ROOT_PRE_DIV_SHIFT;
  1753. *pre_div = val;
  1754. return 0;
  1755. }
  1756. int clock_get_postdiv(enum clk_root_index clock_id,
  1757. enum root_post_div *post_div)
  1758. {
  1759. u32 val, mask;
  1760. int root_entry;
  1761. struct clk_root_map *p;
  1762. void __iomem *clk_root_target;
  1763. if (clock_id >= CLK_ROOT_MAX)
  1764. return -EINVAL;
  1765. root_entry = select(clock_id);
  1766. if (root_entry < 0)
  1767. return -EINVAL;
  1768. p = &root_array[root_entry];
  1769. if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
  1770. (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
  1771. *post_div = 0;
  1772. return 0;
  1773. }
  1774. clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
  1775. if (!clk_root_target)
  1776. return -EINVAL;
  1777. if (p->slice_type == IPG_CLOCK_SLICE)
  1778. mask = CLK_ROOT_IPG_POST_DIV_MASK;
  1779. else if (p->slice_type == CORE_CLOCK_SLICE)
  1780. mask = CLK_ROOT_CORE_POST_DIV_MASK;
  1781. else
  1782. mask = CLK_ROOT_POST_DIV_MASK;
  1783. val = readl(clk_root_target);
  1784. val &= mask;
  1785. val >>= CLK_ROOT_POST_DIV_SHIFT;
  1786. *post_div = val;
  1787. return 0;
  1788. }
  1789. int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
  1790. {
  1791. u32 val;
  1792. int root_entry;
  1793. struct clk_root_map *p;
  1794. void __iomem *clk_root_target;
  1795. if (clock_id >= CLK_ROOT_MAX)
  1796. return -EINVAL;
  1797. root_entry = select(clock_id);
  1798. if (root_entry < 0)
  1799. return -EINVAL;
  1800. p = &root_array[root_entry];
  1801. clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
  1802. if (!clk_root_target)
  1803. return -EINVAL;
  1804. val = readl(clk_root_target);
  1805. val &= CLK_ROOT_SRC_MUX_MASK;
  1806. val >>= CLK_ROOT_SRC_MUX_SHIFT;
  1807. *p_clock_src = p->src_mux[val];
  1808. return 0;
  1809. }