cpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <bootm.h>
  9. #include <common.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/crm_regs.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <imx_thermal.h>
  22. #include <ipu_pixfmt.h>
  23. #include <thermal.h>
  24. #include <sata.h>
  25. #ifdef CONFIG_FSL_ESDHC_IMX
  26. #include <fsl_esdhc_imx.h>
  27. #endif
  28. static u32 reset_cause = -1;
  29. u32 get_imx_reset_cause(void)
  30. {
  31. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  32. if (reset_cause == -1) {
  33. reset_cause = readl(&src_regs->srsr);
  34. /* preserve the value for U-Boot proper */
  35. #if !defined(CONFIG_SPL_BUILD)
  36. writel(reset_cause, &src_regs->srsr);
  37. #endif
  38. }
  39. return reset_cause;
  40. }
  41. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  42. static char *get_reset_cause(void)
  43. {
  44. switch (get_imx_reset_cause()) {
  45. case 0x00001:
  46. case 0x00011:
  47. return "POR";
  48. case 0x00004:
  49. return "CSU";
  50. case 0x00008:
  51. return "IPP USER";
  52. case 0x00010:
  53. #ifdef CONFIG_MX7
  54. return "WDOG1";
  55. #else
  56. return "WDOG";
  57. #endif
  58. case 0x00020:
  59. return "JTAG HIGH-Z";
  60. case 0x00040:
  61. return "JTAG SW";
  62. case 0x00080:
  63. return "WDOG3";
  64. #ifdef CONFIG_MX7
  65. case 0x00100:
  66. return "WDOG4";
  67. case 0x00200:
  68. return "TEMPSENSE";
  69. #elif defined(CONFIG_IMX8M)
  70. case 0x00100:
  71. return "WDOG2";
  72. case 0x00200:
  73. return "TEMPSENSE";
  74. #else
  75. case 0x00100:
  76. return "TEMPSENSE";
  77. case 0x10000:
  78. return "WARM BOOT";
  79. #endif
  80. default:
  81. return "unknown reset";
  82. }
  83. }
  84. #endif
  85. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  86. const char *get_imx_type(u32 imxtype)
  87. {
  88. switch (imxtype) {
  89. case MXC_CPU_IMX8MP:
  90. return "8MP[8]"; /* Quad-core version of the imx8mp */
  91. case MXC_CPU_IMX8MPD:
  92. return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
  93. case MXC_CPU_IMX8MPL:
  94. return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
  95. case MXC_CPU_IMX8MP7:
  96. return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */
  97. case MXC_CPU_IMX8MP6:
  98. return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
  99. case MXC_CPU_IMX8MP5:
  100. return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */
  101. case MXC_CPU_IMX8MN:
  102. return "8MNano Quad"; /* Quad-core version */
  103. case MXC_CPU_IMX8MND:
  104. return "8MNano Dual"; /* Dual-core version */
  105. case MXC_CPU_IMX8MNS:
  106. return "8MNano Solo"; /* Single-core version */
  107. case MXC_CPU_IMX8MNL:
  108. return "8MNano QuadLite"; /* Quad-core Lite version */
  109. case MXC_CPU_IMX8MNDL:
  110. return "8MNano DualLite"; /* Dual-core Lite version */
  111. case MXC_CPU_IMX8MNSL:
  112. return "8MNano SoloLite"; /* Single-core Lite version */
  113. case MXC_CPU_IMX8MM:
  114. return "8MMQ"; /* Quad-core version of the imx8mm */
  115. case MXC_CPU_IMX8MML:
  116. return "8MMQL"; /* Quad-core Lite version of the imx8mm */
  117. case MXC_CPU_IMX8MMD:
  118. return "8MMD"; /* Dual-core version of the imx8mm */
  119. case MXC_CPU_IMX8MMDL:
  120. return "8MMDL"; /* Dual-core Lite version of the imx8mm */
  121. case MXC_CPU_IMX8MMS:
  122. return "8MMS"; /* Single-core version of the imx8mm */
  123. case MXC_CPU_IMX8MMSL:
  124. return "8MMSL"; /* Single-core Lite version of the imx8mm */
  125. case MXC_CPU_IMX8MQ:
  126. return "8MQ"; /* Quad-core version of the imx8mq */
  127. case MXC_CPU_IMX8MQL:
  128. return "8MQLite"; /* Quad-core Lite version of the imx8mq */
  129. case MXC_CPU_IMX8MD:
  130. return "8MD"; /* Dual-core version of the imx8mq */
  131. case MXC_CPU_MX7S:
  132. return "7S"; /* Single-core version of the mx7 */
  133. case MXC_CPU_MX7D:
  134. return "7D"; /* Dual-core version of the mx7 */
  135. case MXC_CPU_MX6QP:
  136. return "6QP"; /* Quad-Plus version of the mx6 */
  137. case MXC_CPU_MX6DP:
  138. return "6DP"; /* Dual-Plus version of the mx6 */
  139. case MXC_CPU_MX6Q:
  140. return "6Q"; /* Quad-core version of the mx6 */
  141. case MXC_CPU_MX6D:
  142. return "6D"; /* Dual-core version of the mx6 */
  143. case MXC_CPU_MX6DL:
  144. return "6DL"; /* Dual Lite version of the mx6 */
  145. case MXC_CPU_MX6SOLO:
  146. return "6SOLO"; /* Solo version of the mx6 */
  147. case MXC_CPU_MX6SL:
  148. return "6SL"; /* Solo-Lite version of the mx6 */
  149. case MXC_CPU_MX6SLL:
  150. return "6SLL"; /* SLL version of the mx6 */
  151. case MXC_CPU_MX6SX:
  152. return "6SX"; /* SoloX version of the mx6 */
  153. case MXC_CPU_MX6UL:
  154. return "6UL"; /* Ultra-Lite version of the mx6 */
  155. case MXC_CPU_MX6ULL:
  156. return "6ULL"; /* ULL version of the mx6 */
  157. case MXC_CPU_MX6ULZ:
  158. return "6ULZ"; /* ULZ version of the mx6 */
  159. case MXC_CPU_MX51:
  160. return "51";
  161. case MXC_CPU_MX53:
  162. return "53";
  163. default:
  164. return "??";
  165. }
  166. }
  167. int print_cpuinfo(void)
  168. {
  169. u32 cpurev;
  170. __maybe_unused u32 max_freq;
  171. cpurev = get_cpu_rev();
  172. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  173. struct udevice *thermal_dev;
  174. int cpu_tmp, minc, maxc, ret;
  175. printf("CPU: Freescale i.MX%s rev%d.%d",
  176. get_imx_type((cpurev & 0x1FF000) >> 12),
  177. (cpurev & 0x000F0) >> 4,
  178. (cpurev & 0x0000F) >> 0);
  179. max_freq = get_cpu_speed_grade_hz();
  180. if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
  181. printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  182. } else {
  183. printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
  184. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  185. }
  186. #else
  187. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  188. get_imx_type((cpurev & 0x1FF000) >> 12),
  189. (cpurev & 0x000F0) >> 4,
  190. (cpurev & 0x0000F) >> 0,
  191. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  192. #endif
  193. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  194. puts("CPU: ");
  195. switch (get_cpu_temp_grade(&minc, &maxc)) {
  196. case TEMP_AUTOMOTIVE:
  197. puts("Automotive temperature grade ");
  198. break;
  199. case TEMP_INDUSTRIAL:
  200. puts("Industrial temperature grade ");
  201. break;
  202. case TEMP_EXTCOMMERCIAL:
  203. puts("Extended Commercial temperature grade ");
  204. break;
  205. default:
  206. puts("Commercial temperature grade ");
  207. break;
  208. }
  209. printf("(%dC to %dC)", minc, maxc);
  210. ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  211. if (!ret) {
  212. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  213. if (!ret)
  214. printf(" at %dC\n", cpu_tmp);
  215. else
  216. debug(" - invalid sensor data\n");
  217. } else {
  218. debug(" - invalid sensor device\n");
  219. }
  220. #endif
  221. printf("Reset cause: %s\n", get_reset_cause());
  222. return 0;
  223. }
  224. #endif
  225. int cpu_eth_init(struct bd_info *bis)
  226. {
  227. int rc = -ENODEV;
  228. #if defined(CONFIG_FEC_MXC)
  229. rc = fecmxc_initialize(bis);
  230. #endif
  231. return rc;
  232. }
  233. #ifdef CONFIG_FSL_ESDHC_IMX
  234. /*
  235. * Initializes on-chip MMC controllers.
  236. * to override, implement board_mmc_init()
  237. */
  238. int cpu_mmc_init(struct bd_info *bis)
  239. {
  240. return fsl_esdhc_mmc_init(bis);
  241. }
  242. #endif
  243. #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
  244. u32 get_ahb_clk(void)
  245. {
  246. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  247. u32 reg, ahb_podf;
  248. reg = __raw_readl(&imx_ccm->cbcdr);
  249. reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
  250. ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
  251. return get_periph_clk() / (ahb_podf + 1);
  252. }
  253. #endif
  254. void arch_preboot_os(void)
  255. {
  256. #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
  257. imx_pcie_remove();
  258. #endif
  259. #if defined(CONFIG_SATA)
  260. if (!is_mx6sdl()) {
  261. sata_remove(0);
  262. #if defined(CONFIG_MX6)
  263. disable_sata_clock();
  264. #endif
  265. }
  266. #endif
  267. #if defined(CONFIG_VIDEO_IPUV3)
  268. /* disable video before launching O/S */
  269. ipuv3_fb_shutdown();
  270. #endif
  271. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  272. lcdif_power_down();
  273. #endif
  274. }
  275. #ifndef CONFIG_IMX8M
  276. void set_chipselect_size(int const cs_size)
  277. {
  278. unsigned int reg;
  279. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  280. reg = readl(&iomuxc_regs->gpr[1]);
  281. switch (cs_size) {
  282. case CS0_128:
  283. reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  284. reg |= 0x5;
  285. break;
  286. case CS0_64M_CS1_64M:
  287. reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  288. reg |= 0x1B;
  289. break;
  290. case CS0_64M_CS1_32M_CS2_32M:
  291. reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  292. reg |= 0x4B;
  293. break;
  294. case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  295. reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  296. reg |= 0x249;
  297. break;
  298. default:
  299. printf("Unknown chip select size: %d\n", cs_size);
  300. break;
  301. }
  302. writel(reg, &iomuxc_regs->gpr[1]);
  303. }
  304. #endif
  305. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
  306. /*
  307. * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  308. * defines a 2-bit SPEED_GRADING
  309. */
  310. #define OCOTP_TESTER3_SPEED_SHIFT 8
  311. enum cpu_speed {
  312. OCOTP_TESTER3_SPEED_GRADE0,
  313. OCOTP_TESTER3_SPEED_GRADE1,
  314. OCOTP_TESTER3_SPEED_GRADE2,
  315. OCOTP_TESTER3_SPEED_GRADE3,
  316. OCOTP_TESTER3_SPEED_GRADE4,
  317. };
  318. u32 get_cpu_speed_grade_hz(void)
  319. {
  320. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  321. struct fuse_bank *bank = &ocotp->bank[1];
  322. struct fuse_bank1_regs *fuse =
  323. (struct fuse_bank1_regs *)bank->fuse_regs;
  324. uint32_t val;
  325. val = readl(&fuse->tester3);
  326. val >>= OCOTP_TESTER3_SPEED_SHIFT;
  327. if (is_imx8mn() || is_imx8mp()) {
  328. val &= 0xf;
  329. return 2300000000 - val * 100000000;
  330. }
  331. if (is_imx8mm())
  332. val &= 0x7;
  333. else
  334. val &= 0x3;
  335. switch(val) {
  336. case OCOTP_TESTER3_SPEED_GRADE0:
  337. return 800000000;
  338. case OCOTP_TESTER3_SPEED_GRADE1:
  339. return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
  340. case OCOTP_TESTER3_SPEED_GRADE2:
  341. return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
  342. case OCOTP_TESTER3_SPEED_GRADE3:
  343. return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
  344. case OCOTP_TESTER3_SPEED_GRADE4:
  345. return 2000000000;
  346. }
  347. return 0;
  348. }
  349. /*
  350. * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
  351. * defines a 2-bit SPEED_GRADING
  352. */
  353. #define OCOTP_TESTER3_TEMP_SHIFT 6
  354. u32 get_cpu_temp_grade(int *minc, int *maxc)
  355. {
  356. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  357. struct fuse_bank *bank = &ocotp->bank[1];
  358. struct fuse_bank1_regs *fuse =
  359. (struct fuse_bank1_regs *)bank->fuse_regs;
  360. uint32_t val;
  361. val = readl(&fuse->tester3);
  362. val >>= OCOTP_TESTER3_TEMP_SHIFT;
  363. val &= 0x3;
  364. if (minc && maxc) {
  365. if (val == TEMP_AUTOMOTIVE) {
  366. *minc = -40;
  367. *maxc = 125;
  368. } else if (val == TEMP_INDUSTRIAL) {
  369. *minc = -40;
  370. *maxc = 105;
  371. } else if (val == TEMP_EXTCOMMERCIAL) {
  372. *minc = -20;
  373. *maxc = 105;
  374. } else {
  375. *minc = 0;
  376. *maxc = 95;
  377. }
  378. }
  379. return val;
  380. }
  381. #endif
  382. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
  383. enum boot_device get_boot_device(void)
  384. {
  385. struct bootrom_sw_info **p =
  386. (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
  387. enum boot_device boot_dev = SD1_BOOT;
  388. u8 boot_type = (*p)->boot_dev_type;
  389. u8 boot_instance = (*p)->boot_dev_instance;
  390. switch (boot_type) {
  391. case BOOT_TYPE_SD:
  392. boot_dev = boot_instance + SD1_BOOT;
  393. break;
  394. case BOOT_TYPE_MMC:
  395. boot_dev = boot_instance + MMC1_BOOT;
  396. break;
  397. case BOOT_TYPE_NAND:
  398. boot_dev = NAND_BOOT;
  399. break;
  400. case BOOT_TYPE_QSPI:
  401. boot_dev = QSPI_BOOT;
  402. break;
  403. case BOOT_TYPE_WEIM:
  404. boot_dev = WEIM_NOR_BOOT;
  405. break;
  406. case BOOT_TYPE_SPINOR:
  407. boot_dev = SPI_NOR_BOOT;
  408. break;
  409. #ifdef CONFIG_IMX8M
  410. case BOOT_TYPE_USB:
  411. boot_dev = USB_BOOT;
  412. break;
  413. #endif
  414. default:
  415. break;
  416. }
  417. return boot_dev;
  418. }
  419. #endif
  420. #ifdef CONFIG_NXP_BOARD_REVISION
  421. int nxp_board_rev(void)
  422. {
  423. /*
  424. * Get Board ID information from OCOTP_GP1[15:8]
  425. * RevA: 0x1
  426. * RevB: 0x2
  427. * RevC: 0x3
  428. */
  429. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  430. struct fuse_bank *bank = &ocotp->bank[4];
  431. struct fuse_bank4_regs *fuse =
  432. (struct fuse_bank4_regs *)bank->fuse_regs;
  433. return (readl(&fuse->gp1) >> 8 & 0x0F);
  434. }
  435. char nxp_board_rev_string(void)
  436. {
  437. const char *rev = "A";
  438. return (*rev + nxp_board_rev() - 1);
  439. }
  440. #endif