vectors.S 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * vectors - Generic ARM exception table code
  4. *
  5. * Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
  6. * Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  7. * Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
  8. * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
  9. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  10. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  11. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  12. * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
  13. */
  14. #include <config.h>
  15. /*
  16. * A macro to allow insertion of an ARM exception vector either
  17. * for the non-boot0 case or by a boot0-header.
  18. */
  19. .macro ARM_VECTORS
  20. #ifdef CONFIG_ARCH_K3
  21. ldr pc, _reset
  22. #else
  23. b reset
  24. #endif
  25. ldr pc, _undefined_instruction
  26. ldr pc, _software_interrupt
  27. ldr pc, _prefetch_abort
  28. ldr pc, _data_abort
  29. ldr pc, _not_used
  30. ldr pc, _irq
  31. ldr pc, _fiq
  32. .endm
  33. /*
  34. *************************************************************************
  35. *
  36. * Symbol _start is referenced elsewhere, so make it global
  37. *
  38. *************************************************************************
  39. */
  40. .globl _start
  41. /*
  42. *************************************************************************
  43. *
  44. * Vectors have their own section so linker script can map them easily
  45. *
  46. *************************************************************************
  47. */
  48. .section ".vectors", "ax"
  49. #if defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
  50. /*
  51. * Various SoCs need something special and SoC-specific up front in
  52. * order to boot, allow them to set that in their boot0.h file and then
  53. * use it here.
  54. *
  55. * To allow a boot0 hook to insert a 'special' sequence after the vector
  56. * table (e.g. for the socfpga), the presence of a boot0 hook supresses
  57. * the below vector table and assumes that the vector table is filled in
  58. * by the boot0 hook. The requirements for a boot0 hook thus are:
  59. * (1) defines '_start:' as appropriate
  60. * (2) inserts the vector table using ARM_VECTORS as appropriate
  61. */
  62. #include <asm/arch/boot0.h>
  63. #else
  64. /*
  65. *************************************************************************
  66. *
  67. * Exception vectors as described in ARM reference manuals
  68. *
  69. * Uses indirect branch to allow reaching handlers anywhere in memory.
  70. *
  71. *************************************************************************
  72. */
  73. _start:
  74. #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
  75. .word CONFIG_SYS_DV_NOR_BOOT_CFG
  76. #endif
  77. ARM_VECTORS
  78. #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
  79. /*
  80. *************************************************************************
  81. *
  82. * Indirect vectors table
  83. *
  84. * Symbols referenced here must be defined somewhere else
  85. *
  86. *************************************************************************
  87. */
  88. .globl _reset
  89. .globl _undefined_instruction
  90. .globl _software_interrupt
  91. .globl _prefetch_abort
  92. .globl _data_abort
  93. .globl _not_used
  94. .globl _irq
  95. .globl _fiq
  96. #ifdef CONFIG_ARCH_K3
  97. _reset: .word reset
  98. #endif
  99. _undefined_instruction: .word undefined_instruction
  100. _software_interrupt: .word software_interrupt
  101. _prefetch_abort: .word prefetch_abort
  102. _data_abort: .word data_abort
  103. _not_used: .word not_used
  104. _irq: .word irq
  105. _fiq: .word fiq
  106. .balignl 16,0xdeadbeef
  107. /*
  108. *************************************************************************
  109. *
  110. * Interrupt handling
  111. *
  112. *************************************************************************
  113. */
  114. /* SPL interrupt handling: just hang */
  115. #ifdef CONFIG_SPL_BUILD
  116. .align 5
  117. undefined_instruction:
  118. software_interrupt:
  119. prefetch_abort:
  120. data_abort:
  121. not_used:
  122. irq:
  123. fiq:
  124. 1:
  125. b 1b /* hang and never return */
  126. #else /* !CONFIG_SPL_BUILD */
  127. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  128. .globl IRQ_STACK_START_IN
  129. IRQ_STACK_START_IN:
  130. #ifdef IRAM_BASE_ADDR
  131. .word IRAM_BASE_ADDR + 0x20
  132. #else
  133. .word 0x0badc0de
  134. #endif
  135. @
  136. @ IRQ stack frame.
  137. @
  138. #define S_FRAME_SIZE 72
  139. #define S_OLD_R0 68
  140. #define S_PSR 64
  141. #define S_PC 60
  142. #define S_LR 56
  143. #define S_SP 52
  144. #define S_IP 48
  145. #define S_FP 44
  146. #define S_R10 40
  147. #define S_R9 36
  148. #define S_R8 32
  149. #define S_R7 28
  150. #define S_R6 24
  151. #define S_R5 20
  152. #define S_R4 16
  153. #define S_R3 12
  154. #define S_R2 8
  155. #define S_R1 4
  156. #define S_R0 0
  157. #define MODE_SVC 0x13
  158. #define I_BIT 0x80
  159. /*
  160. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  161. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  162. */
  163. .macro bad_save_user_regs
  164. @ carve out a frame on current user stack
  165. sub sp, sp, #S_FRAME_SIZE
  166. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  167. ldr r2, IRQ_STACK_START_IN
  168. @ get values for "aborted" pc and cpsr (into parm regs)
  169. ldmia r2, {r2 - r3}
  170. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  171. add r5, sp, #S_SP
  172. mov r1, lr
  173. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  174. mov r0, sp @ save current stack into r0 (param register)
  175. .endm
  176. .macro irq_save_user_regs
  177. sub sp, sp, #S_FRAME_SIZE
  178. stmia sp, {r0 - r12} @ Calling r0-r12
  179. @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  180. add r8, sp, #S_PC
  181. stmdb r8, {sp, lr}^ @ Calling SP, LR
  182. str lr, [r8, #0] @ Save calling PC
  183. mrs r6, spsr
  184. str r6, [r8, #4] @ Save CPSR
  185. str r0, [r8, #8] @ Save OLD_R0
  186. mov r0, sp
  187. .endm
  188. .macro irq_restore_user_regs
  189. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  190. mov r0, r0
  191. ldr lr, [sp, #S_PC] @ Get PC
  192. add sp, sp, #S_FRAME_SIZE
  193. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  194. .endm
  195. .macro get_bad_stack
  196. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  197. str lr, [r13] @ save caller lr in position 0 of saved stack
  198. mrs lr, spsr @ get the spsr
  199. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  200. mov r13, #MODE_SVC @ prepare SVC-Mode
  201. @ msr spsr_c, r13
  202. msr spsr, r13 @ switch modes, make sure moves will execute
  203. mov lr, pc @ capture return pc
  204. movs pc, lr @ jump to next instruction & switch modes.
  205. .endm
  206. .macro get_irq_stack @ setup IRQ stack
  207. ldr sp, IRQ_STACK_START
  208. .endm
  209. .macro get_fiq_stack @ setup FIQ stack
  210. ldr sp, FIQ_STACK_START
  211. .endm
  212. /*
  213. * exception handlers
  214. */
  215. .align 5
  216. undefined_instruction:
  217. get_bad_stack
  218. bad_save_user_regs
  219. bl do_undefined_instruction
  220. .align 5
  221. software_interrupt:
  222. get_bad_stack
  223. bad_save_user_regs
  224. bl do_software_interrupt
  225. .align 5
  226. prefetch_abort:
  227. get_bad_stack
  228. bad_save_user_regs
  229. bl do_prefetch_abort
  230. .align 5
  231. data_abort:
  232. get_bad_stack
  233. bad_save_user_regs
  234. bl do_data_abort
  235. .align 5
  236. not_used:
  237. get_bad_stack
  238. bad_save_user_regs
  239. bl do_not_used
  240. .align 5
  241. irq:
  242. get_bad_stack
  243. bad_save_user_regs
  244. bl do_irq
  245. .align 5
  246. fiq:
  247. get_bad_stack
  248. bad_save_user_regs
  249. bl do_fiq
  250. #endif /* CONFIG_SPL_BUILD */