gic_64.S 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * GIC Initialization Routines.
  4. *
  5. * (C) Copyright 2013
  6. * David Feng <fenghua@phytium.com.cn>
  7. */
  8. #include <asm-offsets.h>
  9. #include <config.h>
  10. #include <linux/linkage.h>
  11. #include <asm/gic.h>
  12. #include <asm/macro.h>
  13. /*************************************************************************
  14. *
  15. * void gic_init_secure(DistributorBase);
  16. *
  17. * Initialize secure copy of GIC at EL3.
  18. *
  19. *************************************************************************/
  20. ENTRY(gic_init_secure)
  21. /*
  22. * Initialize Distributor
  23. * x0: Distributor Base
  24. */
  25. #if defined(CONFIG_GICV3)
  26. mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
  27. /* EnableGrp1S | ARE_S | ARE_NS */
  28. str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
  29. ldr w9, [x0, GICD_TYPER]
  30. and w10, w9, #0x1f /* ITLinesNumber */
  31. cbz w10, 1f /* No SPIs */
  32. add x11, x0, (GICD_IGROUPRn + 4)
  33. add x12, x0, (GICD_IGROUPMODRn + 4)
  34. mov w9, #~0
  35. 0: str w9, [x11], #0x4
  36. str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
  37. sub w10, w10, #0x1
  38. cbnz w10, 0b
  39. #elif defined(CONFIG_GICV2)
  40. mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
  41. str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
  42. ldr w9, [x0, GICD_TYPER]
  43. and w10, w9, #0x1f /* ITLinesNumber */
  44. cbz w10, 1f /* No SPIs */
  45. add x11, x0, GICD_IGROUPRn
  46. mov w9, #~0 /* Config SPIs as Grp1 */
  47. str w9, [x11], #0x4
  48. 0: str w9, [x11], #0x4
  49. sub w10, w10, #0x1
  50. cbnz w10, 0b
  51. ldr x1, =GICC_BASE /* GICC_CTLR */
  52. mov w0, #3 /* EnableGrp0 | EnableGrp1 */
  53. str w0, [x1]
  54. mov w0, #1 << 7 /* allow NS access to GICC_PMR */
  55. str w0, [x1, #4] /* GICC_PMR */
  56. #endif
  57. 1:
  58. ret
  59. ENDPROC(gic_init_secure)
  60. /*************************************************************************
  61. * For Gicv2:
  62. * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
  63. * For Gicv3:
  64. * void gic_init_secure_percpu(ReDistributorBase);
  65. *
  66. * Initialize secure copy of GIC at EL3.
  67. *
  68. *************************************************************************/
  69. ENTRY(gic_init_secure_percpu)
  70. #if defined(CONFIG_GICV3)
  71. /*
  72. * Initialize ReDistributor
  73. * x0: ReDistributor Base
  74. */
  75. mrs x10, mpidr_el1
  76. lsr x9, x10, #32
  77. bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
  78. mov x9, x0
  79. 1: ldr x11, [x9, GICR_TYPER]
  80. lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
  81. cmp w10, w11
  82. b.eq 2f
  83. add x9, x9, #(2 << 16)
  84. b 1b
  85. /* x9: ReDistributor Base Address of Current CPU */
  86. 2: mov w10, #~0x2
  87. ldr w11, [x9, GICR_WAKER]
  88. and w11, w11, w10 /* Clear ProcessorSleep */
  89. str w11, [x9, GICR_WAKER]
  90. dsb st
  91. isb
  92. 3: ldr w10, [x9, GICR_WAKER]
  93. tbnz w10, #2, 3b /* Wait Children be Alive */
  94. add x10, x9, #(1 << 16) /* SGI_Base */
  95. mov w11, #~0
  96. str w11, [x10, GICR_IGROUPRn]
  97. str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
  98. mov w11, #0x1 /* Enable SGI 0 */
  99. str w11, [x10, GICR_ISENABLERn]
  100. switch_el x10, 3f, 2f, 1f
  101. 3:
  102. /* Initialize Cpu Interface */
  103. mrs x10, ICC_SRE_EL3
  104. orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
  105. /* Allow EL2 access to ICC_SRE_EL2 */
  106. msr ICC_SRE_EL3, x10
  107. isb
  108. mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
  109. msr ICC_IGRPEN1_EL3, x10
  110. isb
  111. msr ICC_CTLR_EL3, xzr
  112. isb
  113. 2:
  114. mrs x10, ICC_SRE_EL2
  115. orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
  116. /* Allow EL1 access to ICC_SRE_EL1 */
  117. msr ICC_SRE_EL2, x10
  118. isb
  119. 1:
  120. msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
  121. isb
  122. mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
  123. msr ICC_PMR_EL1, x10
  124. isb
  125. #elif defined(CONFIG_GICV2)
  126. /*
  127. * Initialize SGIs and PPIs
  128. * x0: Distributor Base
  129. * x1: Cpu Interface Base
  130. */
  131. mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
  132. str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
  133. mov w9, #0x1 /* Enable SGI 0 */
  134. str w9, [x0, GICD_ISENABLERn]
  135. /* Initialize Cpu Interface */
  136. mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
  137. /* Enable Ack Group1 Interrupt & */
  138. /* EnableGrp0 & EnableGrp1 */
  139. str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
  140. mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
  141. str w9, [x1, GICC_PMR]
  142. #endif
  143. ret
  144. ENDPROC(gic_init_secure_percpu)
  145. /*************************************************************************
  146. * For Gicv2:
  147. * void gic_kick_secondary_cpus(DistributorBase);
  148. * For Gicv3:
  149. * void gic_kick_secondary_cpus(void);
  150. *
  151. *************************************************************************/
  152. ENTRY(gic_kick_secondary_cpus)
  153. #if defined(CONFIG_GICV3)
  154. mov x9, #(1 << 40)
  155. msr ICC_ASGI1R_EL1, x9
  156. isb
  157. #elif defined(CONFIG_GICV2)
  158. mov w9, #0x8000
  159. movk w9, #0x100, lsl #16
  160. str w9, [x0, GICD_SGIR]
  161. #endif
  162. ret
  163. ENDPROC(gic_kick_secondary_cpus)
  164. /*************************************************************************
  165. * For Gicv2:
  166. * void gic_wait_for_interrupt(CpuInterfaceBase);
  167. * For Gicv3:
  168. * void gic_wait_for_interrupt(void);
  169. *
  170. * Wait for SGI 0 from master.
  171. *
  172. *************************************************************************/
  173. ENTRY(gic_wait_for_interrupt)
  174. #if defined(CONFIG_GICV3)
  175. gic_wait_for_interrupt_m x9
  176. #elif defined(CONFIG_GICV2)
  177. gic_wait_for_interrupt_m x0, w9
  178. #endif
  179. ret
  180. ENDPROC(gic_wait_for_interrupt)