cache-cp15.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <log.h>
  9. #include <asm/system.h>
  10. #include <asm/cache.h>
  11. #include <linux/compiler.h>
  12. #include <asm/armv7_mpu.h>
  13. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #ifdef CONFIG_SYS_ARM_MMU
  16. __weak void arm_init_before_mmu(void)
  17. {
  18. }
  19. __weak void arm_init_domains(void)
  20. {
  21. }
  22. static void set_section_phys(int section, phys_addr_t phys,
  23. enum dcache_option option)
  24. {
  25. #ifdef CONFIG_ARMV7_LPAE
  26. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  27. /* Need to set the access flag to not fault */
  28. u64 value = TTB_SECT_AP | TTB_SECT_AF;
  29. #else
  30. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  31. u32 value = TTB_SECT_AP;
  32. #endif
  33. /* Add the page offset */
  34. value |= phys;
  35. /* Add caching bits */
  36. value |= option;
  37. /* Set PTE */
  38. page_table[section] = value;
  39. }
  40. void set_section_dcache(int section, enum dcache_option option)
  41. {
  42. set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
  43. }
  44. __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  45. {
  46. debug("%s: Warning: not implemented\n", __func__);
  47. }
  48. void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
  49. size_t size, enum dcache_option option)
  50. {
  51. #ifdef CONFIG_ARMV7_LPAE
  52. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  53. #else
  54. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  55. #endif
  56. unsigned long startpt, stoppt;
  57. unsigned long upto, end;
  58. /* div by 2 before start + size to avoid phys_addr_t overflow */
  59. end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
  60. >> (MMU_SECTION_SHIFT - 1);
  61. start = start >> MMU_SECTION_SHIFT;
  62. #ifdef CONFIG_ARMV7_LPAE
  63. debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
  64. option);
  65. #else
  66. debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  67. option);
  68. #endif
  69. for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
  70. set_section_phys(upto, phys, option);
  71. /*
  72. * Make sure range is cache line aligned
  73. * Only CPU maintains page tables, hence it is safe to always
  74. * flush complete cache lines...
  75. */
  76. startpt = (unsigned long)&page_table[start];
  77. startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  78. stoppt = (unsigned long)&page_table[end];
  79. stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  80. mmu_page_table_flush(startpt, stoppt);
  81. }
  82. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  83. enum dcache_option option)
  84. {
  85. mmu_set_region_dcache_behaviour_phys(start, start, size, option);
  86. }
  87. __weak void dram_bank_mmu_setup(int bank)
  88. {
  89. struct bd_info *bd = gd->bd;
  90. int i;
  91. /* bd->bi_dram is available only after relocation */
  92. if ((gd->flags & GD_FLG_RELOC) == 0)
  93. return;
  94. debug("%s: bank: %d\n", __func__, bank);
  95. for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  96. i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  97. (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
  98. i++)
  99. set_section_dcache(i, DCACHE_DEFAULT_OPTION);
  100. }
  101. /* to activate the MMU we need to set up virtual memory: use 1M areas */
  102. static inline void mmu_setup(void)
  103. {
  104. int i;
  105. u32 reg;
  106. arm_init_before_mmu();
  107. /* Set up an identity-mapping for all 4GB, rw for everyone */
  108. for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
  109. set_section_dcache(i, DCACHE_OFF);
  110. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  111. dram_bank_mmu_setup(i);
  112. }
  113. #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
  114. /* Set up 4 PTE entries pointing to our 4 1GB page tables */
  115. for (i = 0; i < 4; i++) {
  116. u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
  117. u64 tpt = gd->arch.tlb_addr + (4096 * i);
  118. page_table[i] = tpt | TTB_PAGETABLE;
  119. }
  120. reg = TTBCR_EAE;
  121. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  122. reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
  123. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  124. reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
  125. #else
  126. reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
  127. #endif
  128. if (is_hyp()) {
  129. /* Set HTCR to enable LPAE */
  130. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  131. : : "r" (reg) : "memory");
  132. /* Set HTTBR0 */
  133. asm volatile("mcrr p15, 4, %0, %1, c2"
  134. :
  135. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  136. : "memory");
  137. /* Set HMAIR */
  138. asm volatile("mcr p15, 4, %0, c10, c2, 0"
  139. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  140. } else {
  141. /* Set TTBCR to enable LPAE */
  142. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  143. : : "r" (reg) : "memory");
  144. /* Set 64-bit TTBR0 */
  145. asm volatile("mcrr p15, 0, %0, %1, c2"
  146. :
  147. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  148. : "memory");
  149. /* Set MAIR */
  150. asm volatile("mcr p15, 0, %0, c10, c2, 0"
  151. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  152. }
  153. #elif defined(CONFIG_CPU_V7A)
  154. if (is_hyp()) {
  155. /* Set HTCR to disable LPAE */
  156. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  157. : : "r" (0) : "memory");
  158. } else {
  159. /* Set TTBCR to disable LPAE */
  160. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  161. : : "r" (0) : "memory");
  162. }
  163. /* Set TTBR0 */
  164. reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
  165. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  166. reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
  167. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  168. reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
  169. #else
  170. reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
  171. #endif
  172. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  173. : : "r" (reg) : "memory");
  174. #else
  175. /* Copy the page table address to cp15 */
  176. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  177. : : "r" (gd->arch.tlb_addr) : "memory");
  178. #endif
  179. /* Set the access control to all-supervisor */
  180. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  181. : : "r" (~0));
  182. arm_init_domains();
  183. /* and enable the mmu */
  184. reg = get_cr(); /* get control reg. */
  185. set_cr(reg | CR_M);
  186. }
  187. static int mmu_enabled(void)
  188. {
  189. return get_cr() & CR_M;
  190. }
  191. #endif /* CONFIG_SYS_ARM_MMU */
  192. /* cache_bit must be either CR_I or CR_C */
  193. static void cache_enable(uint32_t cache_bit)
  194. {
  195. uint32_t reg;
  196. /* The data cache is not active unless the mmu/mpu is enabled too */
  197. #ifdef CONFIG_SYS_ARM_MMU
  198. if ((cache_bit == CR_C) && !mmu_enabled())
  199. mmu_setup();
  200. #elif defined(CONFIG_SYS_ARM_MPU)
  201. if ((cache_bit == CR_C) && !mpu_enabled()) {
  202. printf("Consider enabling MPU before enabling caches\n");
  203. return;
  204. }
  205. #endif
  206. reg = get_cr(); /* get control reg. */
  207. set_cr(reg | cache_bit);
  208. }
  209. /* cache_bit must be either CR_I or CR_C */
  210. static void cache_disable(uint32_t cache_bit)
  211. {
  212. uint32_t reg;
  213. reg = get_cr();
  214. if (cache_bit == CR_C) {
  215. /* if cache isn;t enabled no need to disable */
  216. if ((reg & CR_C) != CR_C)
  217. return;
  218. #ifdef CONFIG_SYS_ARM_MMU
  219. /* if disabling data cache, disable mmu too */
  220. cache_bit |= CR_M;
  221. #endif
  222. }
  223. reg = get_cr();
  224. #ifdef CONFIG_SYS_ARM_MMU
  225. if (cache_bit == (CR_C | CR_M))
  226. #elif defined(CONFIG_SYS_ARM_MPU)
  227. if (cache_bit == CR_C)
  228. #endif
  229. flush_dcache_all();
  230. set_cr(reg & ~cache_bit);
  231. }
  232. #endif
  233. #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  234. void icache_enable(void)
  235. {
  236. return;
  237. }
  238. void icache_disable(void)
  239. {
  240. return;
  241. }
  242. int icache_status(void)
  243. {
  244. return 0; /* always off */
  245. }
  246. #else
  247. void icache_enable(void)
  248. {
  249. cache_enable(CR_I);
  250. }
  251. void icache_disable(void)
  252. {
  253. cache_disable(CR_I);
  254. }
  255. int icache_status(void)
  256. {
  257. return (get_cr() & CR_I) != 0;
  258. }
  259. #endif
  260. #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  261. void dcache_enable(void)
  262. {
  263. return;
  264. }
  265. void dcache_disable(void)
  266. {
  267. return;
  268. }
  269. int dcache_status(void)
  270. {
  271. return 0; /* always off */
  272. }
  273. #else
  274. void dcache_enable(void)
  275. {
  276. cache_enable(CR_C);
  277. }
  278. void dcache_disable(void)
  279. {
  280. cache_disable(CR_C);
  281. }
  282. int dcache_status(void)
  283. {
  284. return (get_cr() & CR_C) != 0;
  285. }
  286. #endif