macro.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * include/asm-arm/macro.h
  4. *
  5. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  6. */
  7. #ifndef __ASM_ARM_MACRO_H__
  8. #define __ASM_ARM_MACRO_H__
  9. #ifdef CONFIG_ARM64
  10. #include <asm/system.h>
  11. #endif
  12. #ifdef __ASSEMBLY__
  13. /*
  14. * These macros provide a convenient way to write 8, 16 and 32 bit data
  15. * to any address.
  16. * Registers r4 and r5 are used, any data in these registers are
  17. * overwritten by the macros.
  18. * The macros are valid for any ARM architecture, they do not implement
  19. * any memory barriers so caution is recommended when using these when the
  20. * caches are enabled or on a multi-core system.
  21. */
  22. .macro write32, addr, data
  23. ldr r4, =\addr
  24. ldr r5, =\data
  25. str r5, [r4]
  26. .endm
  27. .macro write16, addr, data
  28. ldr r4, =\addr
  29. ldrh r5, =\data
  30. strh r5, [r4]
  31. .endm
  32. .macro write8, addr, data
  33. ldr r4, =\addr
  34. ldrb r5, =\data
  35. strb r5, [r4]
  36. .endm
  37. /*
  38. * This macro generates a loop that can be used for delays in the code.
  39. * Register r4 is used, any data in this register is overwritten by the
  40. * macro.
  41. * The macro is valid for any ARM architeture. The actual time spent in the
  42. * loop will vary from CPU to CPU though.
  43. */
  44. .macro wait_timer, time
  45. ldr r4, =\time
  46. 1:
  47. nop
  48. subs r4, r4, #1
  49. bcs 1b
  50. .endm
  51. #ifdef CONFIG_ARM64
  52. /*
  53. * Register aliases.
  54. */
  55. lr .req x30
  56. /*
  57. * Branch according to exception level
  58. */
  59. .macro switch_el, xreg, el3_label, el2_label, el1_label
  60. mrs \xreg, CurrentEL
  61. cmp \xreg, 0xc
  62. b.eq \el3_label
  63. cmp \xreg, 0x8
  64. b.eq \el2_label
  65. cmp \xreg, 0x4
  66. b.eq \el1_label
  67. .endm
  68. /*
  69. * Branch if current processor is a Cortex-A57 core.
  70. */
  71. .macro branch_if_a57_core, xreg, a57_label
  72. mrs \xreg, midr_el1
  73. lsr \xreg, \xreg, #4
  74. and \xreg, \xreg, #0x00000FFF
  75. cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
  76. b.eq \a57_label
  77. .endm
  78. /*
  79. * Branch if current processor is a Cortex-A53 core.
  80. */
  81. .macro branch_if_a53_core, xreg, a53_label
  82. mrs \xreg, midr_el1
  83. lsr \xreg, \xreg, #4
  84. and \xreg, \xreg, #0x00000FFF
  85. cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
  86. b.eq \a53_label
  87. .endm
  88. /*
  89. * Branch if current processor is a slave,
  90. * choose processor with all zero affinity value as the master.
  91. */
  92. .macro branch_if_slave, xreg, slave_label
  93. #ifdef CONFIG_ARMV8_MULTIENTRY
  94. /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
  95. mrs \xreg, mpidr_el1
  96. tst \xreg, #0xff /* Test Affinity 0 */
  97. b.ne \slave_label
  98. lsr \xreg, \xreg, #8
  99. tst \xreg, #0xff /* Test Affinity 1 */
  100. b.ne \slave_label
  101. lsr \xreg, \xreg, #8
  102. tst \xreg, #0xff /* Test Affinity 2 */
  103. b.ne \slave_label
  104. lsr \xreg, \xreg, #16
  105. tst \xreg, #0xff /* Test Affinity 3 */
  106. b.ne \slave_label
  107. #endif
  108. .endm
  109. /*
  110. * Branch if current processor is a master,
  111. * choose processor with all zero affinity value as the master.
  112. */
  113. .macro branch_if_master, xreg1, xreg2, master_label
  114. #ifdef CONFIG_ARMV8_MULTIENTRY
  115. /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
  116. mrs \xreg1, mpidr_el1
  117. lsr \xreg2, \xreg1, #32
  118. lsl \xreg2, \xreg2, #32
  119. lsl \xreg1, \xreg1, #40
  120. lsr \xreg1, \xreg1, #40
  121. orr \xreg1, \xreg1, \xreg2
  122. cbz \xreg1, \master_label
  123. #else
  124. b \master_label
  125. #endif
  126. .endm
  127. /*
  128. * Switch from EL3 to EL2 for ARMv8
  129. * @ep: kernel entry point
  130. * @flag: The execution state flag for lower exception
  131. * level, ES_TO_AARCH64 or ES_TO_AARCH32
  132. * @tmp: temporary register
  133. *
  134. * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
  135. * For loading 64-bit OS, x0 is physical address to the FDT blob.
  136. * They will be passed to the guest.
  137. */
  138. .macro armv8_switch_to_el2_m, ep, flag, tmp
  139. msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
  140. mov \tmp, #CPTR_EL2_RES1
  141. msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
  142. /* Initialize Generic Timers */
  143. msr cntvoff_el2, xzr
  144. /* Initialize SCTLR_EL2
  145. *
  146. * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
  147. * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
  148. * EE,WXN,I,SA,C,A,M to 0
  149. */
  150. ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
  151. SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
  152. SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
  153. SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
  154. msr sctlr_el2, \tmp
  155. mov \tmp, sp
  156. msr sp_el2, \tmp /* Migrate SP */
  157. mrs \tmp, vbar_el3
  158. msr vbar_el2, \tmp /* Migrate VBAR */
  159. /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
  160. cmp \flag, #ES_TO_AARCH32
  161. b.eq 1f
  162. /*
  163. * The next lower exception level is AArch64, 64bit EL2 | HCE |
  164. * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
  165. * and the SMD depends on requirements.
  166. */
  167. #ifdef CONFIG_ARMV8_PSCI
  168. ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
  169. SCR_EL3_RES1 | SCR_EL3_NS_EN)
  170. #else
  171. ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
  172. SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
  173. SCR_EL3_NS_EN)
  174. #endif
  175. #ifdef CONFIG_ARMV8_EA_EL3_FIRST
  176. orr \tmp, \tmp, #SCR_EL3_EA_EN
  177. #endif
  178. msr scr_el3, \tmp
  179. /* Return to the EL2_SP2 mode from EL3 */
  180. ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
  181. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  182. SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
  183. msr spsr_el3, \tmp
  184. msr elr_el3, \ep
  185. eret
  186. 1:
  187. /*
  188. * The next lower exception level is AArch32, 32bit EL2 | HCE |
  189. * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
  190. */
  191. ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
  192. SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
  193. SCR_EL3_NS_EN)
  194. msr scr_el3, \tmp
  195. /* Return to AArch32 Hypervisor mode */
  196. ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
  197. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  198. SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
  199. SPSR_EL_M_HYP)
  200. msr spsr_el3, \tmp
  201. msr elr_el3, \ep
  202. eret
  203. .endm
  204. /*
  205. * Switch from EL2 to EL1 for ARMv8
  206. * @ep: kernel entry point
  207. * @flag: The execution state flag for lower exception
  208. * level, ES_TO_AARCH64 or ES_TO_AARCH32
  209. * @tmp: temporary register
  210. *
  211. * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
  212. * For loading 64-bit OS, x0 is physical address to the FDT blob.
  213. * They will be passed to the guest.
  214. */
  215. .macro armv8_switch_to_el1_m, ep, flag, tmp
  216. /* Initialize Generic Timers */
  217. mrs \tmp, cnthctl_el2
  218. /* Enable EL1 access to timers */
  219. orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
  220. CNTHCTL_EL2_EL1PCTEN_EN)
  221. msr cnthctl_el2, \tmp
  222. msr cntvoff_el2, xzr
  223. /* Initilize MPID/MPIDR registers */
  224. mrs \tmp, midr_el1
  225. msr vpidr_el2, \tmp
  226. mrs \tmp, mpidr_el1
  227. msr vmpidr_el2, \tmp
  228. /* Disable coprocessor traps */
  229. mov \tmp, #CPTR_EL2_RES1
  230. msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
  231. msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
  232. mov \tmp, #CPACR_EL1_FPEN_EN
  233. msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */
  234. /* SCTLR_EL1 initialization
  235. *
  236. * setting RES1 bits (29,28,23,22,20,11) to 1
  237. * and RES0 bits (31,30,27,21,17,13,10,6) +
  238. * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
  239. * CP15BEN,SA0,SA,C,A,M to 0
  240. */
  241. ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
  242. SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
  243. SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
  244. SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
  245. SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
  246. SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
  247. SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
  248. SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
  249. SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
  250. msr sctlr_el1, \tmp
  251. mov \tmp, sp
  252. msr sp_el1, \tmp /* Migrate SP */
  253. mrs \tmp, vbar_el2
  254. msr vbar_el1, \tmp /* Migrate VBAR */
  255. /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
  256. cmp \flag, #ES_TO_AARCH32
  257. b.eq 1f
  258. /* Initialize HCR_EL2 */
  259. ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
  260. msr hcr_el2, \tmp
  261. /* Return to the EL1_SP1 mode from EL2 */
  262. ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
  263. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  264. SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
  265. msr spsr_el2, \tmp
  266. msr elr_el2, \ep
  267. eret
  268. 1:
  269. /* Initialize HCR_EL2 */
  270. ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
  271. msr hcr_el2, \tmp
  272. /* Return to AArch32 Supervisor mode from EL2 */
  273. ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
  274. SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
  275. SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
  276. SPSR_EL_M_SVC)
  277. msr spsr_el2, \tmp
  278. msr elr_el2, \ep
  279. eret
  280. .endm
  281. #if defined(CONFIG_GICV3)
  282. .macro gic_wait_for_interrupt_m xreg1
  283. 0 : wfi
  284. mrs \xreg1, ICC_IAR1_EL1
  285. msr ICC_EOIR1_EL1, \xreg1
  286. cbnz \xreg1, 0b
  287. .endm
  288. #elif defined(CONFIG_GICV2)
  289. .macro gic_wait_for_interrupt_m xreg1, wreg2
  290. 0 : wfi
  291. ldr \wreg2, [\xreg1, GICC_AIAR]
  292. str \wreg2, [\xreg1, GICC_AEOIR]
  293. and \wreg2, \wreg2, #0x3ff
  294. cbnz \wreg2, 0b
  295. .endm
  296. #endif
  297. #endif /* CONFIG_ARM64 */
  298. #endif /* __ASSEMBLY__ */
  299. #endif /* __ASM_ARM_MACRO_H__ */