barriers.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016 ARM Ltd.
  4. *
  5. * ARM and ARM64 barrier instructions
  6. * split from armv7.h to allow sharing between ARM and ARM64
  7. *
  8. * Original copyright in armv7.h was:
  9. * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
  10. *
  11. * Much of the original barrier code was contributed by:
  12. * Valentine Barshak <valentine.barshak@cogentembedded.com>
  13. */
  14. #ifndef __BARRIERS_H__
  15. #define __BARRIERS_H__
  16. #ifndef __ASSEMBLY__
  17. #ifndef CONFIG_ARM64
  18. /*
  19. * CP15 Barrier instructions
  20. * Please note that we have separate barrier instructions in ARMv7
  21. * However, we use the CP15 based instructtions because we use
  22. * -march=armv5 in U-Boot
  23. */
  24. #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
  25. #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
  26. #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
  27. #endif /* !CONFIG_ARM64 */
  28. #if __LINUX_ARM_ARCH__ >= 7
  29. #define ISB asm volatile ("isb sy" : : : "memory")
  30. #define DSB asm volatile ("dsb sy" : : : "memory")
  31. #define DMB asm volatile ("dmb sy" : : : "memory")
  32. #elif __LINUX_ARM_ARCH__ == 6
  33. #define ISB CP15ISB
  34. #define DSB CP15DSB
  35. #define DMB CP15DMB
  36. #else
  37. #define ISB asm volatile ("" : : : "memory")
  38. #define DSB CP15DSB
  39. #define DMB asm volatile ("" : : : "memory")
  40. #endif
  41. #define isb() ISB
  42. #define dsb() DSB
  43. #define dmb() DMB
  44. #endif /* __ASSEMBLY__ */
  45. #endif /* __BARRIERS_H__ */