armv7m.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010,2011
  4. * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
  5. *
  6. * (C) Copyright 2015
  7. * Kamil Lulko, <kamil.lulko@gmail.com>
  8. */
  9. #ifndef ARMV7M_H
  10. #define ARMV7M_H
  11. /* armv7m fixed base addresses */
  12. #define V7M_SCS_BASE 0xE000E000
  13. #define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100)
  14. #define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00)
  15. #define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78)
  16. #define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90)
  17. #define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30)
  18. #define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50)
  19. #define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90)
  20. #define V7M_SCB_VTOR 0x08
  21. #if !defined(__ASSEMBLY__)
  22. struct v7m_scb {
  23. uint32_t cpuid; /* CPUID Base Register */
  24. uint32_t icsr; /* Interrupt Control and State Register */
  25. uint32_t vtor; /* Vector Table Offset Register */
  26. uint32_t aircr; /* App Interrupt and Reset Control Register */
  27. uint32_t scr; /* offset 0x10: System Control Register */
  28. uint32_t ccr; /* offset 0x14: Config and Control Register */
  29. uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
  30. uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
  31. uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
  32. uint32_t shcrs; /* offset 0x24: System Handler Control State */
  33. uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
  34. uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
  35. uint32_t res; /* offset 0x30: reserved */
  36. uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
  37. uint32_t bfar; /* offset 0x38: BusFault Address Reg */
  38. uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */
  39. };
  40. #define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE)
  41. #define V7M_AIRCR_VECTKEY 0x5fa
  42. #define V7M_AIRCR_VECTKEY_SHIFT 16
  43. #define V7M_AIRCR_ENDIAN (1 << 15)
  44. #define V7M_AIRCR_PRIGROUP_SHIFT 8
  45. #define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
  46. #define V7M_AIRCR_SYSRESET (1 << 2)
  47. #define V7M_ICSR_VECTACT_MSK 0xFF
  48. #define V7M_CCR_DCACHE 16
  49. #define V7M_CCR_ICACHE 17
  50. struct v7m_mpu {
  51. uint32_t type; /* Type Register */
  52. uint32_t ctrl; /* Control Register */
  53. uint32_t rnr; /* Region Number Register */
  54. uint32_t rbar; /* Region Base Address Register */
  55. uint32_t rasr; /* Region Attribute and Size Register */
  56. };
  57. #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE)
  58. #endif /* !defined(__ASSEMBLY__) */
  59. #endif /* ARMV7M_H */