mux.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2008
  4. * Texas Instruments, <www.ti.com>
  5. * Syed Mohammed Khasim <x0khasim@ti.com>
  6. */
  7. #ifndef _MUX_H_
  8. #define _MUX_H_
  9. /*
  10. * IEN - Input Enable
  11. * IDIS - Input Disable
  12. * PTD - Pull type Down
  13. * PTU - Pull type Up
  14. * DIS - Pull type selection is inactive
  15. * EN - Pull type selection is active
  16. * SB_LOW - Standby mode configuration: Output low-level
  17. * SB_HI - Standby mode configuration: Output high-level
  18. * SB_HIZ - Standby mode configuration: Output hi-impedence
  19. * SB_PD - Standby mode pull-down enabled
  20. * SB_PU - Standby mode pull-up enabled
  21. * WKEN - Wakeup input enabled
  22. * M0 - Mode 0
  23. */
  24. #define IEN (1 << 8)
  25. #define IDIS (0 << 8)
  26. #define PTU (1 << 4)
  27. #define PTD (0 << 4)
  28. #define EN (1 << 3)
  29. #define DIS (0 << 3)
  30. #define SB_LOW (1 << 9)
  31. #define SB_HI (5 << 9)
  32. #define SB_HIZ (2 << 9)
  33. #define SB_PD (1 << 12)
  34. #define SB_PU (3 << 12)
  35. #define WKEN (1 << 14)
  36. #define M0 0
  37. #define M1 1
  38. #define M2 2
  39. #define M3 3
  40. #define M4 4
  41. #define M5 5
  42. #define M6 6
  43. #define M7 7
  44. /*
  45. * To get the actual address the offset has to be added
  46. * to OMAP34XX_CTRL_BASE
  47. */
  48. /*SDRC*/
  49. #define CONTROL_PADCONF_SDRC_D0 0x0030
  50. #define CONTROL_PADCONF_SDRC_D1 0x0032
  51. #define CONTROL_PADCONF_SDRC_D2 0x0034
  52. #define CONTROL_PADCONF_SDRC_D3 0x0036
  53. #define CONTROL_PADCONF_SDRC_D4 0x0038
  54. #define CONTROL_PADCONF_SDRC_D5 0x003A
  55. #define CONTROL_PADCONF_SDRC_D6 0x003C
  56. #define CONTROL_PADCONF_SDRC_D7 0x003E
  57. #define CONTROL_PADCONF_SDRC_D8 0x0040
  58. #define CONTROL_PADCONF_SDRC_D9 0x0042
  59. #define CONTROL_PADCONF_SDRC_D10 0x0044
  60. #define CONTROL_PADCONF_SDRC_D11 0x0046
  61. #define CONTROL_PADCONF_SDRC_D12 0x0048
  62. #define CONTROL_PADCONF_SDRC_D13 0x004A
  63. #define CONTROL_PADCONF_SDRC_D14 0x004C
  64. #define CONTROL_PADCONF_SDRC_D15 0x004E
  65. #define CONTROL_PADCONF_SDRC_D16 0x0050
  66. #define CONTROL_PADCONF_SDRC_D17 0x0052
  67. #define CONTROL_PADCONF_SDRC_D18 0x0054
  68. #define CONTROL_PADCONF_SDRC_D19 0x0056
  69. #define CONTROL_PADCONF_SDRC_D20 0x0058
  70. #define CONTROL_PADCONF_SDRC_D21 0x005A
  71. #define CONTROL_PADCONF_SDRC_D22 0x005C
  72. #define CONTROL_PADCONF_SDRC_D23 0x005E
  73. #define CONTROL_PADCONF_SDRC_D24 0x0060
  74. #define CONTROL_PADCONF_SDRC_D25 0x0062
  75. #define CONTROL_PADCONF_SDRC_D26 0x0064
  76. #define CONTROL_PADCONF_SDRC_D27 0x0066
  77. #define CONTROL_PADCONF_SDRC_D28 0x0068
  78. #define CONTROL_PADCONF_SDRC_D29 0x006A
  79. #define CONTROL_PADCONF_SDRC_D30 0x006C
  80. #define CONTROL_PADCONF_SDRC_D31 0x006E
  81. #define CONTROL_PADCONF_SDRC_CLK 0x0070
  82. #define CONTROL_PADCONF_SDRC_DQS0 0x0072
  83. #define CONTROL_PADCONF_SDRC_DQS1 0x0074
  84. #define CONTROL_PADCONF_SDRC_DQS2 0x0076
  85. #define CONTROL_PADCONF_SDRC_DQS3 0x0078
  86. #define CONTROL_PADCONF_SDRC_BA0 0x05A0
  87. #define CONTROL_PADCONF_SDRC_BA1 0x05A2
  88. #define CONTROL_PADCONF_SDRC_A0 0x05A4
  89. #define CONTROL_PADCONF_SDRC_A1 0x05A6
  90. #define CONTROL_PADCONF_SDRC_A2 0x05A8
  91. #define CONTROL_PADCONF_SDRC_A3 0x05AA
  92. #define CONTROL_PADCONF_SDRC_A4 0x05AC
  93. #define CONTROL_PADCONF_SDRC_A5 0x05AE
  94. #define CONTROL_PADCONF_SDRC_A6 0x05B0
  95. #define CONTROL_PADCONF_SDRC_A7 0x05B2
  96. #define CONTROL_PADCONF_SDRC_A8 0x05B4
  97. #define CONTROL_PADCONF_SDRC_A9 0x05B6
  98. #define CONTROL_PADCONF_SDRC_A10 0x05B8
  99. #define CONTROL_PADCONF_SDRC_A11 0x05BA
  100. #define CONTROL_PADCONF_SDRC_A12 0x05BC
  101. #define CONTROL_PADCONF_SDRC_A13 0x05BE
  102. #define CONTROL_PADCONF_SDRC_A14 0x05C0
  103. #define CONTROL_PADCONF_SDRC_NCS0 0x05C2
  104. #define CONTROL_PADCONF_SDRC_NCS1 0x05C4
  105. #define CONTROL_PADCONF_SDRC_NCLK 0x05C6
  106. #define CONTROL_PADCONF_SDRC_NRAS 0x05C8
  107. #define CONTROL_PADCONF_SDRC_NCAS 0x05CA
  108. #define CONTROL_PADCONF_SDRC_NWE 0x05CC
  109. #define CONTROL_PADCONF_SDRC_DM0 0x05CE
  110. #define CONTROL_PADCONF_SDRC_DM1 0x05D0
  111. #define CONTROL_PADCONF_SDRC_DM2 0x05D2
  112. #define CONTROL_PADCONF_SDRC_DM3 0x05D4
  113. /*GPMC*/
  114. #define CONTROL_PADCONF_GPMC_A1 0x007A
  115. #define CONTROL_PADCONF_GPMC_A2 0x007C
  116. #define CONTROL_PADCONF_GPMC_A3 0x007E
  117. #define CONTROL_PADCONF_GPMC_A4 0x0080
  118. #define CONTROL_PADCONF_GPMC_A5 0x0082
  119. #define CONTROL_PADCONF_GPMC_A6 0x0084
  120. #define CONTROL_PADCONF_GPMC_A7 0x0086
  121. #define CONTROL_PADCONF_GPMC_A8 0x0088
  122. #define CONTROL_PADCONF_GPMC_A9 0x008A
  123. #define CONTROL_PADCONF_GPMC_A10 0x008C
  124. #define CONTROL_PADCONF_GPMC_A11 0x0264
  125. #define CONTROL_PADCONF_GPMC_D0 0x008E
  126. #define CONTROL_PADCONF_GPMC_D1 0x0090
  127. #define CONTROL_PADCONF_GPMC_D2 0x0092
  128. #define CONTROL_PADCONF_GPMC_D3 0x0094
  129. #define CONTROL_PADCONF_GPMC_D4 0x0096
  130. #define CONTROL_PADCONF_GPMC_D5 0x0098
  131. #define CONTROL_PADCONF_GPMC_D6 0x009A
  132. #define CONTROL_PADCONF_GPMC_D7 0x009C
  133. #define CONTROL_PADCONF_GPMC_D8 0x009E
  134. #define CONTROL_PADCONF_GPMC_D9 0x00A0
  135. #define CONTROL_PADCONF_GPMC_D10 0x00A2
  136. #define CONTROL_PADCONF_GPMC_D11 0x00A4
  137. #define CONTROL_PADCONF_GPMC_D12 0x00A6
  138. #define CONTROL_PADCONF_GPMC_D13 0x00A8
  139. #define CONTROL_PADCONF_GPMC_D14 0x00AA
  140. #define CONTROL_PADCONF_GPMC_D15 0x00AC
  141. #define CONTROL_PADCONF_GPMC_NCS0 0x00AE
  142. #define CONTROL_PADCONF_GPMC_NCS1 0x00B0
  143. #define CONTROL_PADCONF_GPMC_NCS2 0x00B2
  144. #define CONTROL_PADCONF_GPMC_NCS3 0x00B4
  145. #define CONTROL_PADCONF_GPMC_NCS4 0x00B6
  146. #define CONTROL_PADCONF_GPMC_NCS5 0x00B8
  147. #define CONTROL_PADCONF_GPMC_NCS6 0x00BA
  148. #define CONTROL_PADCONF_GPMC_NCS7 0x00BC
  149. #define CONTROL_PADCONF_GPMC_CLK 0x00BE
  150. #define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0
  151. #define CONTROL_PADCONF_GPMC_NOE 0x00C2
  152. #define CONTROL_PADCONF_GPMC_NWE 0x00C4
  153. #define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6
  154. #define CONTROL_PADCONF_GPMC_NBE1 0x00C8
  155. #define CONTROL_PADCONF_GPMC_NWP 0x00CA
  156. #define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
  157. #define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
  158. #define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
  159. #define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
  160. /*DSS*/
  161. #define CONTROL_PADCONF_DSS_PCLK 0x00D4
  162. #define CONTROL_PADCONF_DSS_HSYNC 0x00D6
  163. #define CONTROL_PADCONF_DSS_VSYNC 0x00D8
  164. #define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
  165. #define CONTROL_PADCONF_DSS_DATA0 0x00DC
  166. #define CONTROL_PADCONF_DSS_DATA1 0x00DE
  167. #define CONTROL_PADCONF_DSS_DATA2 0x00E0
  168. #define CONTROL_PADCONF_DSS_DATA3 0x00E2
  169. #define CONTROL_PADCONF_DSS_DATA4 0x00E4
  170. #define CONTROL_PADCONF_DSS_DATA5 0x00E6
  171. #define CONTROL_PADCONF_DSS_DATA6 0x00E8
  172. #define CONTROL_PADCONF_DSS_DATA7 0x00EA
  173. #define CONTROL_PADCONF_DSS_DATA8 0x00EC
  174. #define CONTROL_PADCONF_DSS_DATA9 0x00EE
  175. #define CONTROL_PADCONF_DSS_DATA10 0x00F0
  176. #define CONTROL_PADCONF_DSS_DATA11 0x00F2
  177. #define CONTROL_PADCONF_DSS_DATA12 0x00F4
  178. #define CONTROL_PADCONF_DSS_DATA13 0x00F6
  179. #define CONTROL_PADCONF_DSS_DATA14 0x00F8
  180. #define CONTROL_PADCONF_DSS_DATA15 0x00FA
  181. #define CONTROL_PADCONF_DSS_DATA16 0x00FC
  182. #define CONTROL_PADCONF_DSS_DATA17 0x00FE
  183. #define CONTROL_PADCONF_DSS_DATA18 0x0100
  184. #define CONTROL_PADCONF_DSS_DATA19 0x0102
  185. #define CONTROL_PADCONF_DSS_DATA20 0x0104
  186. #define CONTROL_PADCONF_DSS_DATA21 0x0106
  187. #define CONTROL_PADCONF_DSS_DATA22 0x0108
  188. #define CONTROL_PADCONF_DSS_DATA23 0x010A
  189. /*CAMERA*/
  190. #define CONTROL_PADCONF_CAM_HS 0x010C
  191. #define CONTROL_PADCONF_CAM_VS 0x010E
  192. #define CONTROL_PADCONF_CAM_XCLKA 0x0110
  193. #define CONTROL_PADCONF_CAM_PCLK 0x0112
  194. #define CONTROL_PADCONF_CAM_FLD 0x0114
  195. #define CONTROL_PADCONF_CAM_D0 0x0116
  196. #define CONTROL_PADCONF_CAM_D1 0x0118
  197. #define CONTROL_PADCONF_CAM_D2 0x011A
  198. #define CONTROL_PADCONF_CAM_D3 0x011C
  199. #define CONTROL_PADCONF_CAM_D4 0x011E
  200. #define CONTROL_PADCONF_CAM_D5 0x0120
  201. #define CONTROL_PADCONF_CAM_D6 0x0122
  202. #define CONTROL_PADCONF_CAM_D7 0x0124
  203. #define CONTROL_PADCONF_CAM_D8 0x0126
  204. #define CONTROL_PADCONF_CAM_D9 0x0128
  205. #define CONTROL_PADCONF_CAM_D10 0x012A
  206. #define CONTROL_PADCONF_CAM_D11 0x012C
  207. #define CONTROL_PADCONF_CAM_XCLKB 0x012E
  208. #define CONTROL_PADCONF_CAM_WEN 0x0130
  209. #define CONTROL_PADCONF_CAM_STROBE 0x0132
  210. #define CONTROL_PADCONF_CSI2_DX0 0x0134
  211. #define CONTROL_PADCONF_CSI2_DY0 0x0136
  212. #define CONTROL_PADCONF_CSI2_DX1 0x0138
  213. #define CONTROL_PADCONF_CSI2_DY1 0x013A
  214. /*Audio Interface */
  215. #define CONTROL_PADCONF_MCBSP2_FSX 0x013C
  216. #define CONTROL_PADCONF_MCBSP2_CLKX 0x013E
  217. #define CONTROL_PADCONF_MCBSP2_DR 0x0140
  218. #define CONTROL_PADCONF_MCBSP2_DX 0x0142
  219. #define CONTROL_PADCONF_MMC1_CLK 0x0144
  220. #define CONTROL_PADCONF_MMC1_CMD 0x0146
  221. #define CONTROL_PADCONF_MMC1_DAT0 0x0148
  222. #define CONTROL_PADCONF_MMC1_DAT1 0x014A
  223. #define CONTROL_PADCONF_MMC1_DAT2 0x014C
  224. #define CONTROL_PADCONF_MMC1_DAT3 0x014E
  225. #define CONTROL_PADCONF_MMC1_DAT4 0x0150
  226. #define CONTROL_PADCONF_MMC1_DAT5 0x0152
  227. #define CONTROL_PADCONF_MMC1_DAT6 0x0154
  228. #define CONTROL_PADCONF_MMC1_DAT7 0x0156
  229. /*Wireless LAN */
  230. #define CONTROL_PADCONF_MMC2_CLK 0x0158
  231. #define CONTROL_PADCONF_MMC2_CMD 0x015A
  232. #define CONTROL_PADCONF_MMC2_DAT0 0x015C
  233. #define CONTROL_PADCONF_MMC2_DAT1 0x015E
  234. #define CONTROL_PADCONF_MMC2_DAT2 0x0160
  235. #define CONTROL_PADCONF_MMC2_DAT3 0x0162
  236. #define CONTROL_PADCONF_MMC2_DAT4 0x0164
  237. #define CONTROL_PADCONF_MMC2_DAT5 0x0166
  238. #define CONTROL_PADCONF_MMC2_DAT6 0x0168
  239. #define CONTROL_PADCONF_MMC2_DAT7 0x016A
  240. /*Bluetooth*/
  241. #define CONTROL_PADCONF_MCBSP3_DX 0x016C
  242. #define CONTROL_PADCONF_MCBSP3_DR 0x016E
  243. #define CONTROL_PADCONF_MCBSP3_CLKX 0x0170
  244. #define CONTROL_PADCONF_MCBSP3_FSX 0x0172
  245. #define CONTROL_PADCONF_UART2_CTS 0x0174
  246. #define CONTROL_PADCONF_UART2_RTS 0x0176
  247. #define CONTROL_PADCONF_UART2_TX 0x0178
  248. #define CONTROL_PADCONF_UART2_RX 0x017A
  249. /*Modem Interface */
  250. #define CONTROL_PADCONF_UART1_TX 0x017C
  251. #define CONTROL_PADCONF_UART1_RTS 0x017E
  252. #define CONTROL_PADCONF_UART1_CTS 0x0180
  253. #define CONTROL_PADCONF_UART1_RX 0x0182
  254. #define CONTROL_PADCONF_MCBSP4_CLKX 0x0184
  255. #define CONTROL_PADCONF_MCBSP4_DR 0x0186
  256. #define CONTROL_PADCONF_MCBSP4_DX 0x0188
  257. #define CONTROL_PADCONF_MCBSP4_FSX 0x018A
  258. #define CONTROL_PADCONF_MCBSP1_CLKR 0x018C
  259. #define CONTROL_PADCONF_MCBSP1_FSR 0x018E
  260. #define CONTROL_PADCONF_MCBSP1_DX 0x0190
  261. #define CONTROL_PADCONF_MCBSP1_DR 0x0192
  262. #define CONTROL_PADCONF_MCBSP_CLKS 0x0194
  263. #define CONTROL_PADCONF_MCBSP1_FSX 0x0196
  264. #define CONTROL_PADCONF_MCBSP1_CLKX 0x0198
  265. /*Serial Interface*/
  266. #define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
  267. #define CONTROL_PADCONF_UART3_RTS_SD 0x019C
  268. #define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
  269. #define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
  270. #define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
  271. #define CONTROL_PADCONF_HSUSB0_STP 0x01A4
  272. #define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
  273. #define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
  274. #define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
  275. #define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
  276. #define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
  277. #define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
  278. #define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
  279. #define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
  280. #define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
  281. #define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
  282. #define CONTROL_PADCONF_I2C1_SCL 0x01BA
  283. #define CONTROL_PADCONF_I2C1_SDA 0x01BC
  284. #define CONTROL_PADCONF_I2C2_SCL 0x01BE
  285. #define CONTROL_PADCONF_I2C2_SDA 0x01C0
  286. #define CONTROL_PADCONF_I2C3_SCL 0x01C2
  287. #define CONTROL_PADCONF_I2C3_SDA 0x01C4
  288. #define CONTROL_PADCONF_I2C4_SCL 0x0A00
  289. #define CONTROL_PADCONF_I2C4_SDA 0x0A02
  290. #define CONTROL_PADCONF_HDQ_SIO 0x01C6
  291. #define CONTROL_PADCONF_MCSPI1_CLK 0x01C8
  292. #define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA
  293. #define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC
  294. #define CONTROL_PADCONF_MCSPI1_CS0 0x01CE
  295. #define CONTROL_PADCONF_MCSPI1_CS1 0x01D0
  296. #define CONTROL_PADCONF_MCSPI1_CS2 0x01D2
  297. #define CONTROL_PADCONF_MCSPI1_CS3 0x01D4
  298. #define CONTROL_PADCONF_MCSPI2_CLK 0x01D6
  299. #define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8
  300. #define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA
  301. #define CONTROL_PADCONF_MCSPI2_CS0 0x01DC
  302. #define CONTROL_PADCONF_MCSPI2_CS1 0x01DE
  303. /*Control and debug */
  304. #define CONTROL_PADCONF_SYS_32K 0x0A04
  305. #define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
  306. #define CONTROL_PADCONF_SYS_NIRQ 0x01E0
  307. #define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
  308. #define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
  309. #define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
  310. #define CONTROL_PADCONF_SYS_BOOT3 0x0A10
  311. #define CONTROL_PADCONF_SYS_BOOT4 0x0A12
  312. #define CONTROL_PADCONF_SYS_BOOT5 0x0A14
  313. #define CONTROL_PADCONF_SYS_BOOT6 0x0A16
  314. #define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
  315. #define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
  316. #define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
  317. #define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
  318. #define CONTROL_PADCONF_JTAG_TCK 0x0A1E
  319. #define CONTROL_PADCONF_JTAG_TMS 0x0A20
  320. #define CONTROL_PADCONF_JTAG_TDI 0x0A22
  321. #define CONTROL_PADCONF_JTAG_EMU0 0x0A24
  322. #define CONTROL_PADCONF_JTAG_EMU1 0x0A26
  323. #define CONTROL_PADCONF_ETK_CLK 0x0A28
  324. #define CONTROL_PADCONF_ETK_CTL 0x0A2A
  325. #define CONTROL_PADCONF_ETK_D0 0x0A2C
  326. #define CONTROL_PADCONF_ETK_D1 0x0A2E
  327. #define CONTROL_PADCONF_ETK_D2 0x0A30
  328. #define CONTROL_PADCONF_ETK_D3 0x0A32
  329. #define CONTROL_PADCONF_ETK_D4 0x0A34
  330. #define CONTROL_PADCONF_ETK_D5 0x0A36
  331. #define CONTROL_PADCONF_ETK_D6 0x0A38
  332. #define CONTROL_PADCONF_ETK_D7 0x0A3A
  333. #define CONTROL_PADCONF_ETK_D8 0x0A3C
  334. #define CONTROL_PADCONF_ETK_D9 0x0A3E
  335. #define CONTROL_PADCONF_ETK_D10 0x0A40
  336. #define CONTROL_PADCONF_ETK_D11 0x0A42
  337. #define CONTROL_PADCONF_ETK_D12 0x0A44
  338. #define CONTROL_PADCONF_ETK_D13 0x0A46
  339. #define CONTROL_PADCONF_ETK_D14 0x0A48
  340. #define CONTROL_PADCONF_ETK_D15 0x0A4A
  341. #define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
  342. #define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
  343. #define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
  344. #define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
  345. #define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
  346. #define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
  347. #define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
  348. #define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
  349. #define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
  350. #define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
  351. #define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
  352. #define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
  353. #define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
  354. #define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
  355. #define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
  356. #define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
  357. #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
  358. #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
  359. #define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
  360. #define CONTROL_PADCONF_JTAG_TDO 0x0A50
  361. /*Die to Die */
  362. #define CONTROL_PADCONF_D2D_MCAD0 0x01E4
  363. #define CONTROL_PADCONF_D2D_MCAD1 0x01E6
  364. #define CONTROL_PADCONF_D2D_MCAD2 0x01E8
  365. #define CONTROL_PADCONF_D2D_MCAD3 0x01EA
  366. #define CONTROL_PADCONF_D2D_MCAD4 0x01EC
  367. #define CONTROL_PADCONF_D2D_MCAD5 0x01EE
  368. #define CONTROL_PADCONF_D2D_MCAD6 0x01F0
  369. #define CONTROL_PADCONF_D2D_MCAD7 0x01F2
  370. #define CONTROL_PADCONF_D2D_MCAD8 0x01F4
  371. #define CONTROL_PADCONF_D2D_MCAD9 0x01F6
  372. #define CONTROL_PADCONF_D2D_MCAD10 0x01F8
  373. #define CONTROL_PADCONF_D2D_MCAD11 0x01FA
  374. #define CONTROL_PADCONF_D2D_MCAD12 0x01FC
  375. #define CONTROL_PADCONF_D2D_MCAD13 0x01FE
  376. #define CONTROL_PADCONF_D2D_MCAD14 0x0200
  377. #define CONTROL_PADCONF_D2D_MCAD15 0x0202
  378. #define CONTROL_PADCONF_D2D_MCAD16 0x0204
  379. #define CONTROL_PADCONF_D2D_MCAD17 0x0206
  380. #define CONTROL_PADCONF_D2D_MCAD18 0x0208
  381. #define CONTROL_PADCONF_D2D_MCAD19 0x020A
  382. #define CONTROL_PADCONF_D2D_MCAD20 0x020C
  383. #define CONTROL_PADCONF_D2D_MCAD21 0x020E
  384. #define CONTROL_PADCONF_D2D_MCAD22 0x0210
  385. #define CONTROL_PADCONF_D2D_MCAD23 0x0212
  386. #define CONTROL_PADCONF_D2D_MCAD24 0x0214
  387. #define CONTROL_PADCONF_D2D_MCAD25 0x0216
  388. #define CONTROL_PADCONF_D2D_MCAD26 0x0218
  389. #define CONTROL_PADCONF_D2D_MCAD27 0x021A
  390. #define CONTROL_PADCONF_D2D_MCAD28 0x021C
  391. #define CONTROL_PADCONF_D2D_MCAD29 0x021E
  392. #define CONTROL_PADCONF_D2D_MCAD30 0x0220
  393. #define CONTROL_PADCONF_D2D_MCAD31 0x0222
  394. #define CONTROL_PADCONF_D2D_MCAD32 0x0224
  395. #define CONTROL_PADCONF_D2D_MCAD33 0x0226
  396. #define CONTROL_PADCONF_D2D_MCAD34 0x0228
  397. #define CONTROL_PADCONF_D2D_MCAD35 0x022A
  398. #define CONTROL_PADCONF_D2D_MCAD36 0x022C
  399. #define CONTROL_PADCONF_D2D_CLK26MI 0x022E
  400. #define CONTROL_PADCONF_D2D_NRESPWRON 0x0230
  401. #define CONTROL_PADCONF_D2D_NRESWARM 0x0232
  402. #define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234
  403. #define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236
  404. #define CONTROL_PADCONF_D2D_SPINT 0x0238
  405. #define CONTROL_PADCONF_D2D_FRINT 0x023A
  406. #define CONTROL_PADCONF_D2D_DMAREQ0 0x023C
  407. #define CONTROL_PADCONF_D2D_DMAREQ1 0x023E
  408. #define CONTROL_PADCONF_D2D_DMAREQ2 0x0240
  409. #define CONTROL_PADCONF_D2D_DMAREQ3 0x0242
  410. #define CONTROL_PADCONF_D2D_N3GTRST 0x0244
  411. #define CONTROL_PADCONF_D2D_N3GTDI 0x0246
  412. #define CONTROL_PADCONF_D2D_N3GTDO 0x0248
  413. #define CONTROL_PADCONF_D2D_N3GTMS 0x024A
  414. #define CONTROL_PADCONF_D2D_N3GTCK 0x024C
  415. #define CONTROL_PADCONF_D2D_N3GRTCK 0x024E
  416. #define CONTROL_PADCONF_D2D_MSTDBY 0x0250
  417. #define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C
  418. #define CONTROL_PADCONF_D2D_IDLEREQ 0x0252
  419. #define CONTROL_PADCONF_D2D_IDLEACK 0x0254
  420. #define CONTROL_PADCONF_D2D_MWRITE 0x0256
  421. #define CONTROL_PADCONF_D2D_SWRITE 0x0258
  422. #define CONTROL_PADCONF_D2D_MREAD 0x025A
  423. #define CONTROL_PADCONF_D2D_SREAD 0x025C
  424. #define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E
  425. #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
  426. #define CONTROL_PADCONF_SDRC_CKE0 0x0262
  427. #define CONTROL_PADCONF_SDRC_CKE1 0x0264
  428. /* AM3517 specific mux configuration */
  429. #define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
  430. /* CCDC */
  431. #define CONTROL_PADCONF_CCDC_PCLK 0x01E4
  432. #define CONTROL_PADCONF_CCDC_FIELD 0x01E6
  433. #define CONTROL_PADCONF_CCDC_HD 0x01E8
  434. #define CONTROL_PADCONF_CCDC_VD 0x01EA
  435. #define CONTROL_PADCONF_CCDC_WEN 0x01EC
  436. #define CONTROL_PADCONF_CCDC_DATA0 0x01EE
  437. #define CONTROL_PADCONF_CCDC_DATA1 0x01F0
  438. #define CONTROL_PADCONF_CCDC_DATA2 0x01F2
  439. #define CONTROL_PADCONF_CCDC_DATA3 0x01F4
  440. #define CONTROL_PADCONF_CCDC_DATA4 0x01F6
  441. #define CONTROL_PADCONF_CCDC_DATA5 0x01F8
  442. #define CONTROL_PADCONF_CCDC_DATA6 0x01FA
  443. #define CONTROL_PADCONF_CCDC_DATA7 0x01FC
  444. /* RMII */
  445. #define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
  446. #define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
  447. #define CONTROL_PADCONF_RMII_RXD0 0x0202
  448. #define CONTROL_PADCONF_RMII_RXD1 0x0204
  449. #define CONTROL_PADCONF_RMII_CRS_DV 0x0206
  450. #define CONTROL_PADCONF_RMII_RXER 0x0208
  451. #define CONTROL_PADCONF_RMII_TXD0 0x020A
  452. #define CONTROL_PADCONF_RMII_TXD1 0x020C
  453. #define CONTROL_PADCONF_RMII_TXEN 0x020E
  454. #define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
  455. #define CONTROL_PADCONF_USB0_DRVBUS 0x0212
  456. /* CAN */
  457. #define CONTROL_PADCONF_HECC1_TXD 0x0214
  458. #define CONTROL_PADCONF_HECC1_RXD 0x0216
  459. #define CONTROL_PADCONF_SYS_BOOT7 0x0218
  460. #define CONTROL_PADCONF_SDRC_DQS0N 0x021A
  461. #define CONTROL_PADCONF_SDRC_DQS1N 0x021C
  462. #define CONTROL_PADCONF_SDRC_DQS2N 0x021E
  463. #define CONTROL_PADCONF_SDRC_DQS3N 0x0220
  464. #define CONTROL_PADCONF_STRBEN_DLY0 0x0222
  465. #define CONTROL_PADCONF_STRBEN_DLY1 0x0224
  466. #define CONTROL_PADCONF_SYS_BOOT8 0x0226
  467. /* AM/DM37xx specific */
  468. #define CONTROL_PADCONF_GPIO112 0x0134
  469. #define CONTROL_PADCONF_GPIO113 0x0136
  470. #define CONTROL_PADCONF_GPIO114 0x0138
  471. #define CONTROL_PADCONF_GPIO115 0x013A
  472. #define CONTROL_PADCONF_GPIO127 0x0A54
  473. #define CONTROL_PADCONF_GPIO126 0x0A56
  474. #define CONTROL_PADCONF_GPIO128 0x0A58
  475. #define CONTROL_PADCONF_GPIO129 0x0A5A
  476. /* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
  477. * of the extended drain cells */
  478. #define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
  479. #define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
  480. #define MUX_VAL(OFFSET, VALUE)\
  481. writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
  482. #define CP(x) (CONTROL_PADCONF_##x)
  483. #endif