cpu.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2008
  4. * Texas Instruments, <www.ti.com>
  5. */
  6. #ifndef _CPU_H
  7. #define _CPU_H
  8. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  9. #include <asm/types.h>
  10. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  11. /* Register offsets of common modules */
  12. /* Control */
  13. #ifndef __KERNEL_STRICT_NAMES
  14. #ifndef __ASSEMBLY__
  15. struct ctrl {
  16. u8 res1[0xC0];
  17. u16 gpmc_nadv_ale; /* 0xC0 */
  18. u16 gpmc_noe; /* 0xC2 */
  19. u16 gpmc_nwe; /* 0xC4 */
  20. u8 res2[0x22A];
  21. u32 status; /* 0x2F0 */
  22. u32 gpstatus; /* 0x2F4 */
  23. u8 res3[0x08];
  24. u32 rpubkey_0; /* 0x300 */
  25. u32 rpubkey_1; /* 0x304 */
  26. u32 rpubkey_2; /* 0x308 */
  27. u32 rpubkey_3; /* 0x30C */
  28. u32 rpubkey_4; /* 0x310 */
  29. u8 res4[0x04];
  30. u32 randkey_0; /* 0x318 */
  31. u32 randkey_1; /* 0x31C */
  32. u32 randkey_2; /* 0x320 */
  33. u32 randkey_3; /* 0x324 */
  34. u8 res5[0x124];
  35. u32 ctrl_omap_stat; /* 0x44C */
  36. };
  37. #else /* __ASSEMBLY__ */
  38. #define CONTROL_STATUS 0x2F0
  39. #endif /* __ASSEMBLY__ */
  40. #endif /* __KERNEL_STRICT_NAMES */
  41. #ifndef __KERNEL_STRICT_NAMES
  42. #ifndef __ASSEMBLY__
  43. struct ctrl_id {
  44. u8 res1[0x4];
  45. u32 idcode; /* 0x04 */
  46. u32 prod_id; /* 0x08 */
  47. u32 sku_id; /* 0x0c */
  48. u8 res2[0x08];
  49. u32 die_id_0; /* 0x18 */
  50. u32 die_id_1; /* 0x1C */
  51. u32 die_id_2; /* 0x20 */
  52. u32 die_id_3; /* 0x24 */
  53. };
  54. #endif /* __ASSEMBLY__ */
  55. #endif /* __KERNEL_STRICT_NAMES */
  56. /* boot pin mask */
  57. #define SYSBOOT_MASK 0x1F
  58. /* device speed */
  59. #define SKUID_CLK_MASK 0xf
  60. #define SKUID_CLK_600MHZ 0x0
  61. #define SKUID_CLK_720MHZ 0x8
  62. #define GPMC_BASE (OMAP34XX_GPMC_BASE)
  63. #define GPMC_CONFIG_CS0 0x60
  64. #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
  65. #ifndef __KERNEL_STRICT_NAMES
  66. #ifdef __ASSEMBLY__
  67. #define GPMC_CONFIG1 0x00
  68. #define GPMC_CONFIG2 0x04
  69. #define GPMC_CONFIG3 0x08
  70. #define GPMC_CONFIG4 0x0C
  71. #define GPMC_CONFIG5 0x10
  72. #define GPMC_CONFIG6 0x14
  73. #define GPMC_CONFIG7 0x18
  74. #endif /* __ASSEMBLY__ */
  75. #endif /* __KERNEL_STRICT_NAMES */
  76. /* GPMC Mapping */
  77. #define FLASH_BASE 0x10000000 /* NOR flash, */
  78. /* aligned to 256 Meg */
  79. #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
  80. /* aligned to 64 Meg */
  81. #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
  82. /* aligned to 256 Meg */
  83. #define DEBUG_BASE 0x08000000 /* debug board */
  84. #define NAND_BASE 0x30000000 /* NAND addr */
  85. /* (actual size small port) */
  86. #define ONENAND_MAP 0x20000000 /* OneNand addr */
  87. /* (actual size small port) */
  88. /* SMS */
  89. #ifndef __KERNEL_STRICT_NAMES
  90. #ifndef __ASSEMBLY__
  91. struct sms {
  92. u8 res1[0x10];
  93. u32 sysconfig; /* 0x10 */
  94. u8 res2[0x34];
  95. u32 rg_att0; /* 0x48 */
  96. u8 res3[0x84];
  97. u32 class_arb0; /* 0xD0 */
  98. };
  99. #endif /* __ASSEMBLY__ */
  100. #endif /* __KERNEL_STRICT_NAMES */
  101. #define BURSTCOMPLETE_GROUP7 (0x1 << 31)
  102. /* SDRC */
  103. #ifndef __KERNEL_STRICT_NAMES
  104. #ifndef __ASSEMBLY__
  105. struct sdrc_cs {
  106. u32 mcfg; /* 0x80 || 0xB0 */
  107. u32 mr; /* 0x84 || 0xB4 */
  108. u8 res1[0x4];
  109. u32 emr2; /* 0x8C || 0xBC */
  110. u8 res2[0x14];
  111. u32 rfr_ctrl; /* 0x84 || 0xD4 */
  112. u32 manual; /* 0xA8 || 0xD8 */
  113. u8 res3[0x4];
  114. };
  115. struct sdrc_actim {
  116. u32 ctrla; /* 0x9C || 0xC4 */
  117. u32 ctrlb; /* 0xA0 || 0xC8 */
  118. };
  119. struct sdrc {
  120. u8 res1[0x10];
  121. u32 sysconfig; /* 0x10 */
  122. u32 status; /* 0x14 */
  123. u8 res2[0x28];
  124. u32 cs_cfg; /* 0x40 */
  125. u32 sharing; /* 0x44 */
  126. u8 res3[0x18];
  127. u32 dlla_ctrl; /* 0x60 */
  128. u32 dlla_status; /* 0x64 */
  129. u32 dllb_ctrl; /* 0x68 */
  130. u32 dllb_status; /* 0x6C */
  131. u32 power; /* 0x70 */
  132. u8 res4[0xC];
  133. struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
  134. };
  135. /* EMIF4 */
  136. typedef struct emif4 {
  137. unsigned int emif_mod_id_rev;
  138. unsigned int sdram_sts;
  139. unsigned int sdram_config;
  140. unsigned int res1;
  141. unsigned int sdram_refresh_ctrl;
  142. unsigned int sdram_refresh_ctrl_shdw;
  143. unsigned int sdram_time1;
  144. unsigned int sdram_time1_shdw;
  145. unsigned int sdram_time2;
  146. unsigned int sdram_time2_shdw;
  147. unsigned int sdram_time3;
  148. unsigned int sdram_time3_shdw;
  149. unsigned char res2[8];
  150. unsigned int sdram_pwr_mgmt;
  151. unsigned int sdram_pwr_mgmt_shdw;
  152. unsigned char res3[32];
  153. unsigned int sdram_iodft_tlgc;
  154. unsigned char res4[128];
  155. unsigned int ddr_phyctrl1;
  156. unsigned int ddr_phyctrl1_shdw;
  157. unsigned int ddr_phyctrl2;
  158. } emif4_t;
  159. #endif /* __ASSEMBLY__ */
  160. #endif /* __KERNEL_STRICT_NAMES */
  161. #define DLLPHASE_90 (0x1 << 1)
  162. #define LOADDLL (0x1 << 2)
  163. #define ENADLL (0x1 << 3)
  164. #define DLL_DELAY_MASK 0xFF00
  165. #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
  166. #define PAGEPOLICY_HIGH (0x1 << 0)
  167. #define SRFRONRESET (0x1 << 7)
  168. #define PWDNEN (0x1 << 2)
  169. #define WAKEUPPROC (0x1 << 26)
  170. #define DDR_SDRAM (0x1 << 0)
  171. #define DEEPPD (0x1 << 3)
  172. #define B32NOT16 (0x1 << 4)
  173. #define BANKALLOCATION (0x2 << 6)
  174. #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
  175. #define ADDRMUXLEGACY (0x1 << 19)
  176. #define CASWIDTH_10BITS (0x5 << 20)
  177. #define RASWIDTH_13BITS (0x2 << 24)
  178. #define BURSTLENGTH4 (0x2 << 0)
  179. #define CASL3 (0x3 << 4)
  180. #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
  181. #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
  182. #define ARE_ARCV_1 (0x1 << 0)
  183. #define ARCV (0x4e2 << 8) /* Autorefresh count */
  184. #define OMAP34XX_SDRC_CS0 0x80000000
  185. #define OMAP34XX_SDRC_CS1 0xA0000000
  186. #define CMD_NOP 0x0
  187. #define CMD_PRECHARGE 0x1
  188. #define CMD_AUTOREFRESH 0x2
  189. #define CMD_ENTR_PWRDOWN 0x3
  190. #define CMD_EXIT_PWRDOWN 0x4
  191. #define CMD_ENTR_SRFRSH 0x5
  192. #define CMD_CKE_HIGH 0x6
  193. #define CMD_CKE_LOW 0x7
  194. #define SOFTRESET (0x1 << 1)
  195. #define SMART_IDLE (0x2 << 3)
  196. #define REF_ON_IDLE (0x1 << 6)
  197. /* DMA */
  198. #ifndef __KERNEL_STRICT_NAMES
  199. #ifndef __ASSEMBLY__
  200. struct dma4_chan {
  201. u32 ccr;
  202. u32 clnk_ctrl;
  203. u32 cicr;
  204. u32 csr;
  205. u32 csdp;
  206. u32 cen;
  207. u32 cfn;
  208. u32 cssa;
  209. u32 cdsa;
  210. u32 csel;
  211. u32 csfl;
  212. u32 cdel;
  213. u32 cdfl;
  214. u32 csac;
  215. u32 cdac;
  216. u32 ccen;
  217. u32 ccfn;
  218. u32 color;
  219. };
  220. struct dma4 {
  221. u32 revision;
  222. u8 res1[0x4];
  223. u32 irqstatus_l[0x4];
  224. u32 irqenable_l[0x4];
  225. u32 sysstatus;
  226. u32 ocp_sysconfig;
  227. u8 res2[0x34];
  228. u32 caps_0;
  229. u8 res3[0x4];
  230. u32 caps_2;
  231. u32 caps_3;
  232. u32 caps_4;
  233. u32 gcr;
  234. u8 res4[0x4];
  235. struct dma4_chan chan[32];
  236. };
  237. #endif /*__ASSEMBLY__ */
  238. #endif /* __KERNEL_STRICT_NAMES */
  239. /* timer regs offsets (32 bit regs) */
  240. #ifndef __KERNEL_STRICT_NAMES
  241. #ifndef __ASSEMBLY__
  242. struct gptimer {
  243. u32 tidr; /* 0x00 r */
  244. u8 res[0xc];
  245. u32 tiocp_cfg; /* 0x10 rw */
  246. u32 tistat; /* 0x14 r */
  247. u32 tisr; /* 0x18 rw */
  248. u32 tier; /* 0x1c rw */
  249. u32 twer; /* 0x20 rw */
  250. u32 tclr; /* 0x24 rw */
  251. u32 tcrr; /* 0x28 rw */
  252. u32 tldr; /* 0x2c rw */
  253. u32 ttgr; /* 0x30 rw */
  254. u32 twpc; /* 0x34 r*/
  255. u32 tmar; /* 0x38 rw*/
  256. u32 tcar1; /* 0x3c r */
  257. u32 tcicr; /* 0x40 rw */
  258. u32 tcar2; /* 0x44 r */
  259. };
  260. #endif /* __ASSEMBLY__ */
  261. #endif /* __KERNEL_STRICT_NAMES */
  262. /* enable sys_clk NO-prescale /1 */
  263. #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
  264. /* Watchdog */
  265. #ifndef __KERNEL_STRICT_NAMES
  266. #ifndef __ASSEMBLY__
  267. struct watchdog {
  268. u8 res1[0x34];
  269. u32 wwps; /* 0x34 r */
  270. u8 res2[0x10];
  271. u32 wspr; /* 0x48 rw */
  272. };
  273. #endif /* __ASSEMBLY__ */
  274. #endif /* __KERNEL_STRICT_NAMES */
  275. #define WD_UNLOCK1 0xAAAA
  276. #define WD_UNLOCK2 0x5555
  277. /* PRCM */
  278. #define PRCM_BASE 0x48004000
  279. #ifndef __KERNEL_STRICT_NAMES
  280. #ifndef __ASSEMBLY__
  281. struct prcm {
  282. u32 fclken_iva2; /* 0x00 */
  283. u32 clken_pll_iva2; /* 0x04 */
  284. u8 res1[0x1c];
  285. u32 idlest_pll_iva2; /* 0x24 */
  286. u8 res2[0x18];
  287. u32 clksel1_pll_iva2 ; /* 0x40 */
  288. u32 clksel2_pll_iva2; /* 0x44 */
  289. u8 res3[0x8bc];
  290. u32 clken_pll_mpu; /* 0x904 */
  291. u8 res4[0x1c];
  292. u32 idlest_pll_mpu; /* 0x924 */
  293. u8 res5[0x18];
  294. u32 clksel1_pll_mpu; /* 0x940 */
  295. u32 clksel2_pll_mpu; /* 0x944 */
  296. u8 res6[0xb8];
  297. u32 fclken1_core; /* 0xa00 */
  298. u32 res_fclken2_core;
  299. u32 fclken3_core; /* 0xa08 */
  300. u8 res7[0x4];
  301. u32 iclken1_core; /* 0xa10 */
  302. u32 iclken2_core; /* 0xa14 */
  303. u32 iclken3_core; /* 0xa18 */
  304. u8 res8[0x24];
  305. u32 clksel_core; /* 0xa40 */
  306. u8 res9[0xbc];
  307. u32 fclken_gfx; /* 0xb00 */
  308. u8 res10[0xc];
  309. u32 iclken_gfx; /* 0xb10 */
  310. u8 res11[0x2c];
  311. u32 clksel_gfx; /* 0xb40 */
  312. u8 res12[0xbc];
  313. u32 fclken_wkup; /* 0xc00 */
  314. u8 res13[0xc];
  315. u32 iclken_wkup; /* 0xc10 */
  316. u8 res14[0xc];
  317. u32 idlest_wkup; /* 0xc20 */
  318. u8 res15[0x1c];
  319. u32 clksel_wkup; /* 0xc40 */
  320. u8 res16[0xbc];
  321. u32 clken_pll; /* 0xd00 */
  322. u32 clken2_pll; /* 0xd04 */
  323. u8 res17[0x18];
  324. u32 idlest_ckgen; /* 0xd20 */
  325. u32 idlest2_ckgen; /* 0xd24 */
  326. u8 res18[0x18];
  327. u32 clksel1_pll; /* 0xd40 */
  328. u32 clksel2_pll; /* 0xd44 */
  329. u32 clksel3_pll; /* 0xd48 */
  330. u32 clksel4_pll; /* 0xd4c */
  331. u32 clksel5_pll; /* 0xd50 */
  332. u8 res19[0xac];
  333. u32 fclken_dss; /* 0xe00 */
  334. u8 res20[0xc];
  335. u32 iclken_dss; /* 0xe10 */
  336. u8 res21[0x2c];
  337. u32 clksel_dss; /* 0xe40 */
  338. u8 res22[0xbc];
  339. u32 fclken_cam; /* 0xf00 */
  340. u8 res23[0xc];
  341. u32 iclken_cam; /* 0xf10 */
  342. u8 res24[0x2c];
  343. u32 clksel_cam; /* 0xf40 */
  344. u8 res25[0xbc];
  345. u32 fclken_per; /* 0x1000 */
  346. u8 res26[0xc];
  347. u32 iclken_per; /* 0x1010 */
  348. u8 res27[0x2c];
  349. u32 clksel_per; /* 0x1040 */
  350. u8 res28[0xfc];
  351. u32 clksel1_emu; /* 0x1140 */
  352. u8 res29[0x2bc];
  353. u32 fclken_usbhost; /* 0x1400 */
  354. u8 res30[0xc];
  355. u32 iclken_usbhost; /* 0x1410 */
  356. };
  357. #else /* __ASSEMBLY__ */
  358. #define CM_CLKSEL_CORE 0x48004a40
  359. #define CM_CLKSEL_GFX 0x48004b40
  360. #define CM_CLKSEL_WKUP 0x48004c40
  361. #define CM_CLKEN_PLL 0x48004d00
  362. #define CM_CLKSEL1_PLL 0x48004d40
  363. #define CM_CLKSEL1_EMU 0x48005140
  364. #endif /* __ASSEMBLY__ */
  365. #endif /* __KERNEL_STRICT_NAMES */
  366. #define PRM_BASE 0x48306000
  367. #ifndef __KERNEL_STRICT_NAMES
  368. #ifndef __ASSEMBLY__
  369. struct prm {
  370. u8 res1[0xd40];
  371. u32 clksel; /* 0xd40 */
  372. u8 res2[0x50c];
  373. u32 rstctrl; /* 0x1250 */
  374. u8 res3[0x1c];
  375. u32 clksrc_ctrl; /* 0x1270 */
  376. };
  377. #endif /* __ASSEMBLY__ */
  378. #endif /* __KERNEL_STRICT_NAMES */
  379. #define PRM_RSTCTRL 0x48307250
  380. #define PRM_RSTCTRL_RESET 0x04
  381. #define PRM_RSTST 0x48307258
  382. #define PRM_RSTST_WARM_RESET_MASK 0x7D2
  383. #define SYSCLKDIV_1 (0x1 << 6)
  384. #define SYSCLKDIV_2 (0x1 << 7)
  385. #define CLKSEL_GPT1 (0x1 << 0)
  386. #define EN_GPT1 (0x1 << 0)
  387. #define EN_32KSYNC (0x1 << 2)
  388. #define ST_WDT2 (0x1 << 5)
  389. #define ST_MPU_CLK (0x1 << 0)
  390. #define ST_CORE_CLK (0x1 << 0)
  391. #define ST_PERIPH_CLK (0x1 << 1)
  392. #define ST_IVA2_CLK (0x1 << 0)
  393. #define RESETDONE (0x1 << 0)
  394. #define TCLR_ST (0x1 << 0)
  395. #define TCLR_AR (0x1 << 1)
  396. #define TCLR_PRE (0x1 << 5)
  397. /* SMX-APE */
  398. #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
  399. #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
  400. #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
  401. #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
  402. #ifndef __KERNEL_STRICT_NAMES
  403. #ifndef __ASSEMBLY__
  404. struct pm {
  405. u8 res1[0x48];
  406. u32 req_info_permission_0; /* 0x48 */
  407. u8 res2[0x4];
  408. u32 read_permission_0; /* 0x50 */
  409. u8 res3[0x4];
  410. u32 wirte_permission_0; /* 0x58 */
  411. u8 res4[0x4];
  412. u32 addr_match_1; /* 0x58 */
  413. u8 res5[0x4];
  414. u32 req_info_permission_1; /* 0x68 */
  415. u8 res6[0x14];
  416. u32 addr_match_2; /* 0x80 */
  417. };
  418. #endif /*__ASSEMBLY__ */
  419. #endif /* __KERNEL_STRICT_NAMES */
  420. /* Permission values for registers -Full fledged permissions to all */
  421. #define UNLOCK_1 0xFFFFFFFF
  422. #define UNLOCK_2 0x00000000
  423. #define UNLOCK_3 0x0000FFFF
  424. #define NOT_EARLY 0
  425. /* I2C base */
  426. #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
  427. #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
  428. #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
  429. /* MUSB base */
  430. #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
  431. /* OMAP3 GPIO registers */
  432. #define OMAP_GPIO_REVISION 0x0000
  433. #define OMAP_GPIO_SYSCONFIG 0x0010
  434. #define OMAP_GPIO_SYSSTATUS 0x0014
  435. #define OMAP_GPIO_IRQSTATUS1 0x0018
  436. #define OMAP_GPIO_IRQSTATUS2 0x0028
  437. #define OMAP_GPIO_IRQENABLE2 0x002c
  438. #define OMAP_GPIO_IRQENABLE1 0x001c
  439. #define OMAP_GPIO_WAKE_EN 0x0020
  440. #define OMAP_GPIO_CTRL 0x0030
  441. #define OMAP_GPIO_OE 0x0034
  442. #define OMAP_GPIO_DATAIN 0x0038
  443. #define OMAP_GPIO_DATAOUT 0x003c
  444. #define OMAP_GPIO_LEVELDETECT0 0x0040
  445. #define OMAP_GPIO_LEVELDETECT1 0x0044
  446. #define OMAP_GPIO_RISINGDETECT 0x0048
  447. #define OMAP_GPIO_FALLINGDETECT 0x004c
  448. #define OMAP_GPIO_DEBOUNCE_EN 0x0050
  449. #define OMAP_GPIO_DEBOUNCE_VAL 0x0054
  450. #define OMAP_GPIO_CLEARIRQENABLE1 0x0060
  451. #define OMAP_GPIO_SETIRQENABLE1 0x0064
  452. #define OMAP_GPIO_CLEARWKUENA 0x0080
  453. #define OMAP_GPIO_SETWKUENA 0x0084
  454. #define OMAP_GPIO_CLEARDATAOUT 0x0090
  455. #define OMAP_GPIO_SETDATAOUT 0x0094
  456. #endif /* _CPU_H */