clocks_omap3.h 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2008
  4. * Texas Instruments, <www.ti.com>
  5. * Richard Woodruff <r-woodruff2@ti.com>
  6. */
  7. #ifndef _CLOCKS_OMAP3_H_
  8. #define _CLOCKS_OMAP3_H_
  9. #define PLL_STOP 1 /* PER & IVA */
  10. #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
  11. #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
  12. #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
  13. /*
  14. * The following configurations are OPP and SysClk value independant
  15. * and hence are defined here. All the other DPLL related values are
  16. * tabulated in lowlevel_init.S.
  17. */
  18. /* CORE DPLL */
  19. #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
  20. #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
  21. #define CORE_FUSB_DIV 2 /* 41.5MHz: */
  22. #define CORE_L4_DIV 2 /* 83MHz : L4 */
  23. #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
  24. #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
  25. #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
  26. #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
  27. /* PER DPLL */
  28. #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
  29. #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
  30. #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
  31. #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
  32. #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
  33. /* MPU DPLL */
  34. #define MPU_M_12_ES1 0x0FE
  35. #define MPU_N_12_ES1 0x07
  36. #define MPU_FSEL_12_ES1 0x05
  37. #define MPU_M2_12_ES1 0x01
  38. #define MPU_M_12_ES2 0x0FA
  39. #define MPU_N_12_ES2 0x05
  40. #define MPU_FSEL_12_ES2 0x07
  41. #define MPU_M2_ES2 0x01
  42. #define MPU_M_12 0x085
  43. #define MPU_N_12 0x05
  44. #define MPU_FSEL_12 0x07
  45. #define MPU_M2_12 0x01
  46. #define MPU_M_13_ES1 0x17D
  47. #define MPU_N_13_ES1 0x0C
  48. #define MPU_FSEL_13_ES1 0x03
  49. #define MPU_M2_13_ES1 0x01
  50. #define MPU_M_13_ES2 0x258
  51. #define MPU_N_13_ES2 0x0C
  52. #define MPU_FSEL_13_ES2 0x03
  53. #define MPU_M2_13_ES2 0x01
  54. #define MPU_M_13 0x10A
  55. #define MPU_N_13 0x0C
  56. #define MPU_FSEL_13 0x03
  57. #define MPU_M2_13 0x01
  58. #define MPU_M_19P2_ES1 0x179
  59. #define MPU_N_19P2_ES1 0x12
  60. #define MPU_FSEL_19P2_ES1 0x04
  61. #define MPU_M2_19P2_ES1 0x01
  62. #define MPU_M_19P2_ES2 0x271
  63. #define MPU_N_19P2_ES2 0x17
  64. #define MPU_FSEL_19P2_ES2 0x03
  65. #define MPU_M2_19P2_ES2 0x01
  66. #define MPU_M_19P2 0x14C
  67. #define MPU_N_19P2 0x17
  68. #define MPU_FSEL_19P2 0x03
  69. #define MPU_M2_19P2 0x01
  70. #define MPU_M_26_ES1 0x17D
  71. #define MPU_N_26_ES1 0x19
  72. #define MPU_FSEL_26_ES1 0x03
  73. #define MPU_M2_26_ES1 0x01
  74. #define MPU_M_26_ES2 0x0FA
  75. #define MPU_N_26_ES2 0x0C
  76. #define MPU_FSEL_26_ES2 0x07
  77. #define MPU_M2_26_ES2 0x01
  78. #define MPU_M_26 0x085
  79. #define MPU_N_26 0x0C
  80. #define MPU_FSEL_26 0x07
  81. #define MPU_M2_26 0x01
  82. #define MPU_M_38P4_ES1 0x1FA
  83. #define MPU_N_38P4_ES1 0x32
  84. #define MPU_FSEL_38P4_ES1 0x03
  85. #define MPU_M2_38P4_ES1 0x01
  86. #define MPU_M_38P4_ES2 0x271
  87. #define MPU_N_38P4_ES2 0x2F
  88. #define MPU_FSEL_38P4_ES2 0x03
  89. #define MPU_M2_38P4_ES2 0x01
  90. #define MPU_M_38P4 0x14C
  91. #define MPU_N_38P4 0x2F
  92. #define MPU_FSEL_38P4 0x03
  93. #define MPU_M2_38P4 0x01
  94. /* IVA DPLL */
  95. #define IVA_M_12_ES1 0x07D
  96. #define IVA_N_12_ES1 0x05
  97. #define IVA_FSEL_12_ES1 0x07
  98. #define IVA_M2_12_ES1 0x01
  99. #define IVA_M_12_ES2 0x0B4
  100. #define IVA_N_12_ES2 0x05
  101. #define IVA_FSEL_12_ES2 0x07
  102. #define IVA_M2_12_ES2 0x01
  103. #define IVA_M_12 0x085
  104. #define IVA_N_12 0x05
  105. #define IVA_FSEL_12 0x07
  106. #define IVA_M2_12 0x01
  107. #define IVA_M_13_ES1 0x0FA
  108. #define IVA_N_13_ES1 0x0C
  109. #define IVA_FSEL_13_ES1 0x03
  110. #define IVA_M2_13_ES1 0x01
  111. #define IVA_M_13_ES2 0x168
  112. #define IVA_N_13_ES2 0x0C
  113. #define IVA_FSEL_13_ES2 0x03
  114. #define IVA_M2_13_ES2 0x01
  115. #define IVA_M_13 0x10A
  116. #define IVA_N_13 0x0C
  117. #define IVA_FSEL_13 0x03
  118. #define IVA_M2_13 0x01
  119. #define IVA_M_19P2_ES1 0x082
  120. #define IVA_N_19P2_ES1 0x09
  121. #define IVA_FSEL_19P2_ES1 0x07
  122. #define IVA_M2_19P2_ES1 0x01
  123. #define IVA_M_19P2_ES2 0x0E1
  124. #define IVA_N_19P2_ES2 0x0B
  125. #define IVA_FSEL_19P2_ES2 0x06
  126. #define IVA_M2_19P2_ES2 0x01
  127. #define IVA_M_19P2 0x14C
  128. #define IVA_N_19P2 0x17
  129. #define IVA_FSEL_19P2 0x03
  130. #define IVA_M2_19P2 0x01
  131. #define IVA_M_26_ES1 0x07D
  132. #define IVA_N_26_ES1 0x0C
  133. #define IVA_FSEL_26_ES1 0x07
  134. #define IVA_M2_26_ES1 0x01
  135. #define IVA_M_26_ES2 0x0B4
  136. #define IVA_N_26_ES2 0x0C
  137. #define IVA_FSEL_26_ES2 0x07
  138. #define IVA_M2_26_ES2 0x01
  139. #define IVA_M_26 0x085
  140. #define IVA_N_26 0x0C
  141. #define IVA_FSEL_26 0x07
  142. #define IVA_M2_26 0x01
  143. #define IVA_M_38P4_ES1 0x13F
  144. #define IVA_N_38P4_ES1 0x30
  145. #define IVA_FSEL_38P4_ES1 0x03
  146. #define IVA_M2_38P4_ES1 0x01
  147. #define IVA_M_38P4_ES2 0x0E1
  148. #define IVA_N_38P4_ES2 0x17
  149. #define IVA_FSEL_38P4_ES2 0x06
  150. #define IVA_M2_38P4_ES2 0x01
  151. #define IVA_M_38P4 0x14C
  152. #define IVA_N_38P4 0x2F
  153. #define IVA_FSEL_38P4 0x03
  154. #define IVA_M2_38P4 0x01
  155. /* CORE DPLL */
  156. #define CORE_M_12 0xA6
  157. #define CORE_N_12 0x05
  158. #define CORE_FSEL_12 0x07
  159. #define CORE_M2_12 0x01 /* M3 of 2 */
  160. #define CORE_M_12_ES1 0x19F
  161. #define CORE_N_12_ES1 0x0E
  162. #define CORE_FSL_12_ES1 0x03
  163. #define CORE_M2_12_ES1 0x1 /* M3 of 2 */
  164. #define CORE_M_13 0x14C
  165. #define CORE_N_13 0x0C
  166. #define CORE_FSEL_13 0x03
  167. #define CORE_M2_13 0x01 /* M3 of 2 */
  168. #define CORE_M_13_ES1 0x1B2
  169. #define CORE_N_13_ES1 0x10
  170. #define CORE_FSL_13_ES1 0x03
  171. #define CORE_M2_13_ES1 0x01 /* M3 of 2 */
  172. #define CORE_M_19P2 0x19F
  173. #define CORE_N_19P2 0x17
  174. #define CORE_FSEL_19P2 0x03
  175. #define CORE_M2_19P2 0x01 /* M3 of 2 */
  176. #define CORE_M_19P2_ES1 0x19F
  177. #define CORE_N_19P2_ES1 0x17
  178. #define CORE_FSL_19P2_ES1 0x03
  179. #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
  180. #define CORE_M_26 0xA6
  181. #define CORE_N_26 0x0C
  182. #define CORE_FSEL_26 0x07
  183. #define CORE_M2_26 0x01 /* M3 of 2 */
  184. #define CORE_M_26_ES1 0x1B2
  185. #define CORE_N_26_ES1 0x21
  186. #define CORE_FSL_26_ES1 0x03
  187. #define CORE_M2_26_ES1 0x01 /* M3 of 2 */
  188. #define CORE_M_38P4 0x19F
  189. #define CORE_N_38P4 0x2F
  190. #define CORE_FSEL_38P4 0x03
  191. #define CORE_M2_38P4 0x01 /* M3 of 2 */
  192. #define CORE_M_38P4_ES1 0x19F
  193. #define CORE_N_38P4_ES1 0x2F
  194. #define CORE_FSL_38P4_ES1 0x03
  195. #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
  196. /* PER DPLL */
  197. #define PER_M_12 0xD8
  198. #define PER_N_12 0x05
  199. #define PER_FSEL_12 0x07
  200. #define PER_M2_12 0x09
  201. #define PER_M_13 0x1B0
  202. #define PER_N_13 0x0C
  203. #define PER_FSEL_13 0x03
  204. #define PER_M2_13 0x09
  205. #define PER_M_19P2 0xE1
  206. #define PER_N_19P2 0x09
  207. #define PER_FSEL_19P2 0x07
  208. #define PER_M2_19P2 0x09
  209. #define PER_M_26 0xD8
  210. #define PER_N_26 0x0C
  211. #define PER_FSEL_26 0x07
  212. #define PER_M2_26 0x09
  213. #define PER_M_38P4 0xE1
  214. #define PER_N_38P4 0x13
  215. #define PER_FSEL_38P4 0x07
  216. #define PER_M2_38P4 0x09
  217. /* PER2 DPLL */
  218. #define PER2_M_12 0x78
  219. #define PER2_N_12 0x0B
  220. #define PER2_FSEL_12 0x03
  221. #define PER2_M2_12 0x01
  222. #define PER2_M_13 0x78
  223. #define PER2_N_13 0x0C
  224. #define PER2_FSEL_13 0x03
  225. #define PER2_M2_13 0x01
  226. #define PER2_M_19P2 0x2EE
  227. #define PER2_N_19P2 0x0B
  228. #define PER2_FSEL_19P2 0x06
  229. #define PER2_M2_19P2 0x0A
  230. #define PER2_M_26 0x78
  231. #define PER2_N_26 0x0C
  232. #define PER2_FSEL_26 0x03
  233. #define PER2_M2_26 0x01
  234. #define PER2_M_38P4 0x2EE
  235. #define PER2_N_38P4 0x0B
  236. #define PER2_FSEL_38P4 0x06
  237. #define PER2_M2_38P4 0x0A
  238. /* 36XX PER DPLL */
  239. #define PER_36XX_M_12 0x1B0
  240. #define PER_36XX_N_12 0x05
  241. #define PER_36XX_FSEL_12 0x07
  242. #define PER_36XX_M2_12 0x09
  243. #define PER_36XX_M_13 0x360
  244. #define PER_36XX_N_13 0x0C
  245. #define PER_36XX_FSEL_13 0x03
  246. #define PER_36XX_M2_13 0x09
  247. #define PER_36XX_M_19P2 0x1C2
  248. #define PER_36XX_N_19P2 0x09
  249. #define PER_36XX_FSEL_19P2 0x07
  250. #define PER_36XX_M2_19P2 0x09
  251. #define PER_36XX_M_26 0x1B0
  252. #define PER_36XX_N_26 0x0C
  253. #define PER_36XX_FSEL_26 0x07
  254. #define PER_36XX_M2_26 0x09
  255. #define PER_36XX_M_38P4 0x1C2
  256. #define PER_36XX_N_38P4 0x13
  257. #define PER_36XX_FSEL_38P4 0x07
  258. #define PER_36XX_M2_38P4 0x09
  259. /* 36XX PER2 DPLL */
  260. #define PER2_36XX_M_12 0x50
  261. #define PER2_36XX_N_12 0x00
  262. #define PER2_36XX_M2_12 0x08
  263. #define PER2_36XX_M_13 0x1BB
  264. #define PER2_36XX_N_13 0x05
  265. #define PER2_36XX_M2_13 0x08
  266. #define PER2_36XX_M_19P2 0x32
  267. #define PER2_36XX_N_19P2 0x00
  268. #define PER2_36XX_M2_19P2 0x08
  269. #define PER2_36XX_M_26 0x1BB
  270. #define PER2_36XX_N_26 0x0B
  271. #define PER2_36XX_M2_26 0x08
  272. #define PER2_36XX_M_38P4 0x19
  273. #define PER2_36XX_N_38P4 0x00
  274. #define PER2_36XX_M2_38P4 0x08
  275. #endif /* endif _CLOCKS_OMAP3_H_ */