sys_proto.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX23/i.MX28 specific functions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #ifndef __MXS_SYS_PROTO_H__
  9. #define __MXS_SYS_PROTO_H__
  10. #include <asm/mach-imx/sys_proto.h>
  11. int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
  12. int (*cd)(int));
  13. #ifdef CONFIG_SPL_BUILD
  14. #if defined(CONFIG_MX23)
  15. #include <asm/arch/iomux-mx23.h>
  16. #elif defined(CONFIG_MX28)
  17. #include <asm/arch/iomux-mx28.h>
  18. #endif
  19. void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
  20. const iomux_cfg_t *iomux_setup,
  21. const unsigned int iomux_size);
  22. void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
  23. #endif
  24. struct mxs_pair {
  25. uint8_t boot_pads;
  26. uint8_t boot_mask;
  27. const char *mode;
  28. };
  29. static const struct mxs_pair mxs_boot_modes[] = {
  30. #if defined(CONFIG_MX23)
  31. { 0x00, 0x0f, "USB" },
  32. { 0x01, 0x1f, "I2C, master" },
  33. { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
  34. { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
  35. { 0x04, 0x1f, "NAND" },
  36. { 0x06, 0x1f, "JTAG" },
  37. { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
  38. { 0x09, 0x1f, "SSP SD/MMC #0" },
  39. { 0x0a, 0x1f, "SSP SD/MMC #1" },
  40. { 0x00, 0x00, "Reserved/Unknown/Wrong" },
  41. #elif defined(CONFIG_MX28)
  42. { 0x00, 0x0f, "USB #0" },
  43. { 0x01, 0x1f, "I2C #0, master, 3V3" },
  44. { 0x11, 0x1f, "I2C #0, master, 1V8" },
  45. { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
  46. { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
  47. { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
  48. { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
  49. { 0x04, 0x1f, "NAND, 3V3" },
  50. { 0x14, 0x1f, "NAND, 1V8" },
  51. { 0x06, 0x1f, "JTAG" },
  52. { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
  53. { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
  54. { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
  55. { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
  56. { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
  57. { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
  58. { 0x00, 0x00, "Reserved/Unknown/Wrong" },
  59. #endif
  60. };
  61. #define MXS_BM_USB 0x00
  62. #define MXS_BM_I2C_MASTER_3V3 0x01
  63. #define MXS_BM_I2C_MASTER_1V8 0x11
  64. #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
  65. #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
  66. #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
  67. #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
  68. #define MXS_BM_NAND_3V3 0x04
  69. #define MXS_BM_NAND_1V8 0x14
  70. #define MXS_BM_JTAG 0x06
  71. #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
  72. #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
  73. #define MXS_BM_SDMMC0_3V3 0x09
  74. #define MXS_BM_SDMMC0_1V8 0x19
  75. #define MXS_BM_SDMMC1_3V3 0x0a
  76. #define MXS_BM_SDMMC1_1V8 0x1a
  77. #define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200))
  78. struct mxs_spl_data {
  79. uint8_t boot_mode_idx;
  80. uint32_t mem_dram_size;
  81. };
  82. int mxs_dram_init(void);
  83. #endif /* __SYS_PROTO_H__ */