regs-usb.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 USB OTG Register Definitions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #ifndef __REGS_USB_H__
  9. #define __REGS_USB_H__
  10. struct mxs_usb_regs {
  11. uint32_t hw_usbctrl_id; /* 0x000 */
  12. uint32_t hw_usbctrl_hwgeneral; /* 0x004 */
  13. uint32_t hw_usbctrl_hwhost; /* 0x008 */
  14. uint32_t hw_usbctrl_hwdevice; /* 0x00c */
  15. uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */
  16. uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */
  17. uint32_t reserved1[26];
  18. uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */
  19. uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */
  20. uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */
  21. uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */
  22. uint32_t hw_usbctrl_sbuscfg; /* 0x090 */
  23. uint32_t reserved2[27];
  24. uint32_t hw_usbctrl_caplength; /* 0x100 */
  25. uint32_t hw_usbctrl_hcsparams; /* 0x104 */
  26. uint32_t hw_usbctrl_hccparams; /* 0x108 */
  27. uint32_t reserved3[5];
  28. uint32_t hw_usbctrl_dciversion; /* 0x120 */
  29. uint32_t hw_usbctrl_dccparams; /* 0x124 */
  30. uint32_t reserved4[6];
  31. uint32_t hw_usbctrl_usbcmd; /* 0x140 */
  32. uint32_t hw_usbctrl_usbsts; /* 0x144 */
  33. uint32_t hw_usbctrl_usbintr; /* 0x148 */
  34. uint32_t hw_usbctrl_frindex; /* 0x14c */
  35. uint32_t reserved5;
  36. union {
  37. uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */
  38. uint32_t hw_usbctrl_deviceaddr; /* 0x154 */
  39. };
  40. union {
  41. uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */
  42. uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */
  43. };
  44. uint32_t hw_usbctrl_ttctrl; /* 0x15c */
  45. uint32_t hw_usbctrl_burstsize; /* 0x160 */
  46. uint32_t hw_usbctrl_txfilltuning; /* 0x164 */
  47. uint32_t reserved6;
  48. uint32_t hw_usbctrl_ic_usb; /* 0x16c */
  49. uint32_t hw_usbctrl_ulpi; /* 0x170 */
  50. uint32_t reserved7;
  51. uint32_t hw_usbctrl_endptnak; /* 0x178 */
  52. uint32_t hw_usbctrl_endptnaken; /* 0x17c */
  53. uint32_t reserved8;
  54. uint32_t hw_usbctrl_portsc1; /* 0x184 */
  55. uint32_t reserved9[7];
  56. uint32_t hw_usbctrl_otgsc; /* 0x1a4 */
  57. uint32_t hw_usbctrl_usbmode; /* 0x1a8 */
  58. uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */
  59. uint32_t hw_usbctrl_endptprime; /* 0x1b0 */
  60. uint32_t hw_usbctrl_endptflush; /* 0x1b4 */
  61. uint32_t hw_usbctrl_endptstat; /* 0x1b8 */
  62. uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */
  63. uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */
  64. uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */
  65. uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */
  66. uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */
  67. uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */
  68. uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */
  69. uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */
  70. uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */
  71. };
  72. #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
  73. #define HW_USBCTRL_ID_CIVERSION_OFFSET 29
  74. #define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29)
  75. #define HW_USBCTRL_ID_VERSION_OFFSET 25
  76. #define HW_USBCTRL_ID_VERSION_MASK (0xf << 25)
  77. #define HW_USBCTRL_ID_REVISION_OFFSET 21
  78. #define HW_USBCTRL_ID_REVISION_MASK (0xf << 21)
  79. #define HW_USBCTRL_ID_TAG_OFFSET 16
  80. #define HW_USBCTRL_ID_TAG_MASK (0x1f << 16)
  81. #define HW_USBCTRL_ID_NID_OFFSET 8
  82. #define HW_USBCTRL_ID_NID_MASK (0x3f << 8)
  83. #define HW_USBCTRL_ID_ID_OFFSET 0
  84. #define HW_USBCTRL_ID_ID_MASK (0x3f << 0)
  85. #define HW_USBCTRL_HWGENERAL_SM_OFFSET 9
  86. #define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9)
  87. #define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6
  88. #define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6)
  89. #define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4
  90. #define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4)
  91. #define HW_USBCTRL_HWGENERAL_BWT (1 << 3)
  92. #define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1
  93. #define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1)
  94. #define HW_USBCTRL_HWGENERAL_RT (1 << 0)
  95. #define HW_USBCTRL_HWHOST_TTPER_OFFSET 24
  96. #define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24)
  97. #define HW_USBCTRL_HWHOST_TTASY_OFFSET 16
  98. #define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19)
  99. #define HW_USBCTRL_HWHOST_NPORT_OFFSET 1
  100. #define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1)
  101. #define HW_USBCTRL_HWHOST_HC (1 << 0)
  102. #define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1
  103. #define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1)
  104. #define HW_USBCTRL_HWDEVICE_DC (1 << 0)
  105. #define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31)
  106. #define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16
  107. #define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16)
  108. #define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8
  109. #define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8)
  110. #define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0
  111. #define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff
  112. #define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8
  113. #define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8)
  114. #define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0
  115. #define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff
  116. #define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0
  117. #define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff
  118. #define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31)
  119. #define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30)
  120. #define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24)
  121. #define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0
  122. #define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff
  123. #define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0
  124. #define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7
  125. #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0
  126. #define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1
  127. #define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2
  128. #define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3
  129. #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5
  130. #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6
  131. #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7
  132. #endif /* __REGS_USB_H__ */