regs-ssp.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 SSP Register Definitions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on code from LTIB:
  8. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  9. */
  10. #ifndef __MX28_REGS_SSP_H__
  11. #define __MX28_REGS_SSP_H__
  12. #include <asm/mach-imx/regs-common.h>
  13. #ifndef __ASSEMBLY__
  14. #if defined(CONFIG_MX23)
  15. struct mxs_ssp_regs {
  16. mxs_reg_32(hw_ssp_ctrl0)
  17. mxs_reg_32(hw_ssp_cmd0)
  18. mxs_reg_32(hw_ssp_cmd1)
  19. mxs_reg_32(hw_ssp_compref)
  20. mxs_reg_32(hw_ssp_compmask)
  21. mxs_reg_32(hw_ssp_timing)
  22. mxs_reg_32(hw_ssp_ctrl1)
  23. mxs_reg_32(hw_ssp_data)
  24. mxs_reg_32(hw_ssp_sdresp0)
  25. mxs_reg_32(hw_ssp_sdresp1)
  26. mxs_reg_32(hw_ssp_sdresp2)
  27. mxs_reg_32(hw_ssp_sdresp3)
  28. mxs_reg_32(hw_ssp_status)
  29. uint32_t reserved1[12];
  30. mxs_reg_32(hw_ssp_debug)
  31. mxs_reg_32(hw_ssp_version)
  32. };
  33. #elif defined(CONFIG_MX28)
  34. struct mxs_ssp_regs {
  35. mxs_reg_32(hw_ssp_ctrl0)
  36. mxs_reg_32(hw_ssp_cmd0)
  37. mxs_reg_32(hw_ssp_cmd1)
  38. mxs_reg_32(hw_ssp_xfer_size)
  39. mxs_reg_32(hw_ssp_block_size)
  40. mxs_reg_32(hw_ssp_compref)
  41. mxs_reg_32(hw_ssp_compmask)
  42. mxs_reg_32(hw_ssp_timing)
  43. mxs_reg_32(hw_ssp_ctrl1)
  44. mxs_reg_32(hw_ssp_data)
  45. mxs_reg_32(hw_ssp_sdresp0)
  46. mxs_reg_32(hw_ssp_sdresp1)
  47. mxs_reg_32(hw_ssp_sdresp2)
  48. mxs_reg_32(hw_ssp_sdresp3)
  49. mxs_reg_32(hw_ssp_ddr_ctrl)
  50. mxs_reg_32(hw_ssp_dll_ctrl)
  51. mxs_reg_32(hw_ssp_status)
  52. mxs_reg_32(hw_ssp_dll_sts)
  53. mxs_reg_32(hw_ssp_debug)
  54. mxs_reg_32(hw_ssp_version)
  55. };
  56. #endif
  57. static inline int mxs_ssp_bus_id_valid(int bus)
  58. {
  59. #if defined(CONFIG_MX23)
  60. const unsigned int mxs_ssp_chan_count = 2;
  61. #elif defined(CONFIG_MX28)
  62. const unsigned int mxs_ssp_chan_count = 4;
  63. #endif
  64. if (bus >= mxs_ssp_chan_count)
  65. return 0;
  66. if (bus < 0)
  67. return 0;
  68. return 1;
  69. }
  70. static inline int mxs_ssp_clock_by_bus(unsigned int clock)
  71. {
  72. #if defined(CONFIG_MX23)
  73. return 0;
  74. #elif defined(CONFIG_MX28)
  75. return clock;
  76. #endif
  77. }
  78. static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
  79. {
  80. switch (port) {
  81. case 0:
  82. return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
  83. case 1:
  84. return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
  85. #ifdef CONFIG_MX28
  86. case 2:
  87. return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
  88. case 3:
  89. return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
  90. #endif
  91. default:
  92. return NULL;
  93. }
  94. }
  95. #endif
  96. #define SSP_CTRL0_SFTRST (1 << 31)
  97. #define SSP_CTRL0_CLKGATE (1 << 30)
  98. #define SSP_CTRL0_RUN (1 << 29)
  99. #define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
  100. #define SSP_CTRL0_LOCK_CS (1 << 27)
  101. #define SSP_CTRL0_IGNORE_CRC (1 << 26)
  102. #define SSP_CTRL0_READ (1 << 25)
  103. #define SSP_CTRL0_DATA_XFER (1 << 24)
  104. #define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22)
  105. #define SSP_CTRL0_BUS_WIDTH_OFFSET 22
  106. #define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22)
  107. #define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22)
  108. #define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22)
  109. #define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
  110. #define SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
  111. #define SSP_CTRL0_LONG_RESP (1 << 19)
  112. #define SSP_CTRL0_CHECK_RESP (1 << 18)
  113. #define SSP_CTRL0_GET_RESP (1 << 17)
  114. #define SSP_CTRL0_ENABLE (1 << 16)
  115. #ifdef CONFIG_MX23
  116. #define SSP_CTRL0_XFER_COUNT_OFFSET 0
  117. #define SSP_CTRL0_XFER_COUNT_MASK 0xffff
  118. #endif
  119. #define SSP_CMD0_SOFT_TERMINATE (1 << 26)
  120. #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
  121. #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24)
  122. #define SSP_CMD0_BOOT_ACK_EN (1 << 23)
  123. #define SSP_CMD0_SLOW_CLKING_EN (1 << 22)
  124. #define SSP_CMD0_CONT_CLKING_EN (1 << 21)
  125. #define SSP_CMD0_APPEND_8CYC (1 << 20)
  126. #if defined(CONFIG_MX23)
  127. #define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16)
  128. #define SSP_CMD0_BLOCK_SIZE_OFFSET 16
  129. #define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8)
  130. #define SSP_CMD0_BLOCK_COUNT_OFFSET 8
  131. #endif
  132. #define SSP_CMD0_CMD_MASK 0xff
  133. #define SSP_CMD0_CMD_OFFSET 0
  134. #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00
  135. #define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01
  136. #define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02
  137. #define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03
  138. #define SSP_CMD0_CMD_MMC_SET_DSR 0x04
  139. #define SSP_CMD0_CMD_MMC_RESERVED_5 0x05
  140. #define SSP_CMD0_CMD_MMC_SWITCH 0x06
  141. #define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07
  142. #define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08
  143. #define SSP_CMD0_CMD_MMC_SEND_CSD 0x09
  144. #define SSP_CMD0_CMD_MMC_SEND_CID 0x0a
  145. #define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b
  146. #define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c
  147. #define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d
  148. #define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e
  149. #define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f
  150. #define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10
  151. #define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11
  152. #define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12
  153. #define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13
  154. #define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14
  155. #define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17
  156. #define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18
  157. #define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19
  158. #define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a
  159. #define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b
  160. #define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c
  161. #define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d
  162. #define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e
  163. #define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23
  164. #define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24
  165. #define SSP_CMD0_CMD_MMC_ERASE 0x26
  166. #define SSP_CMD0_CMD_MMC_FAST_IO 0x27
  167. #define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28
  168. #define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a
  169. #define SSP_CMD0_CMD_MMC_APP_CMD 0x37
  170. #define SSP_CMD0_CMD_MMC_GEN_CMD 0x38
  171. #define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00
  172. #define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02
  173. #define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03
  174. #define SSP_CMD0_CMD_SD_SET_DSR 0x04
  175. #define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05
  176. #define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07
  177. #define SSP_CMD0_CMD_SD_SEND_CSD 0x09
  178. #define SSP_CMD0_CMD_SD_SEND_CID 0x0a
  179. #define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c
  180. #define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d
  181. #define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f
  182. #define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10
  183. #define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11
  184. #define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12
  185. #define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18
  186. #define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19
  187. #define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b
  188. #define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c
  189. #define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d
  190. #define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e
  191. #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20
  192. #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21
  193. #define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23
  194. #define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24
  195. #define SSP_CMD0_CMD_SD_ERASE 0x26
  196. #define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a
  197. #define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34
  198. #define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35
  199. #define SSP_CMD0_CMD_SD_APP_CMD 0x37
  200. #define SSP_CMD0_CMD_SD_GEN_CMD 0x38
  201. #define SSP_CMD1_CMD_ARG_MASK 0xffffffff
  202. #define SSP_CMD1_CMD_ARG_OFFSET 0
  203. #if defined(CONFIG_MX28)
  204. #define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff
  205. #define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0
  206. #define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4)
  207. #define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4
  208. #define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf
  209. #define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0
  210. #endif
  211. #define SSP_COMPREF_REFERENCE_MASK 0xffffffff
  212. #define SSP_COMPREF_REFERENCE_OFFSET 0
  213. #define SSP_COMPMASK_MASK_MASK 0xffffffff
  214. #define SSP_COMPMASK_MASK_OFFSET 0
  215. #define SSP_TIMING_TIMEOUT_MASK (0xffff << 16)
  216. #define SSP_TIMING_TIMEOUT_OFFSET 16
  217. #define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8)
  218. #define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8
  219. #define SSP_TIMING_CLOCK_RATE_MASK 0xff
  220. #define SSP_TIMING_CLOCK_RATE_OFFSET 0
  221. #define SSP_CTRL1_SDIO_IRQ (1 << 31)
  222. #define SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
  223. #define SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
  224. #define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
  225. #define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
  226. #define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
  227. #define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
  228. #define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
  229. #define SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
  230. #define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
  231. #define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
  232. #define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20)
  233. #define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19)
  234. #define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18)
  235. #define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
  236. #define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
  237. #define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
  238. #define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
  239. #define SSP_CTRL1_DMA_ENABLE (1 << 13)
  240. #define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12)
  241. #define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11)
  242. #define SSP_CTRL1_PHASE (1 << 10)
  243. #define SSP_CTRL1_POLARITY (1 << 9)
  244. #define SSP_CTRL1_SLAVE_MODE (1 << 8)
  245. #define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4)
  246. #define SSP_CTRL1_WORD_LENGTH_OFFSET 4
  247. #define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4)
  248. #define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4)
  249. #define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4)
  250. #define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4)
  251. #define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4)
  252. #define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4)
  253. #define SSP_CTRL1_SSP_MODE_MASK 0xf
  254. #define SSP_CTRL1_SSP_MODE_OFFSET 0
  255. #define SSP_CTRL1_SSP_MODE_SPI 0x0
  256. #define SSP_CTRL1_SSP_MODE_SSI 0x1
  257. #define SSP_CTRL1_SSP_MODE_SD_MMC 0x3
  258. #define SSP_CTRL1_SSP_MODE_MS 0x4
  259. #define SSP_DATA_DATA_MASK 0xffffffff
  260. #define SSP_DATA_DATA_OFFSET 0
  261. #define SSP_SDRESP0_RESP0_MASK 0xffffffff
  262. #define SSP_SDRESP0_RESP0_OFFSET 0
  263. #define SSP_SDRESP1_RESP1_MASK 0xffffffff
  264. #define SSP_SDRESP1_RESP1_OFFSET 0
  265. #define SSP_SDRESP2_RESP2_MASK 0xffffffff
  266. #define SSP_SDRESP2_RESP2_OFFSET 0
  267. #define SSP_SDRESP3_RESP3_MASK 0xffffffff
  268. #define SSP_SDRESP3_RESP3_OFFSET 0
  269. #define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30)
  270. #define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30
  271. #define SSP_DDR_CTRL_NIBBLE_POS (1 << 1)
  272. #define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0)
  273. #define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28)
  274. #define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28
  275. #define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20)
  276. #define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20
  277. #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10)
  278. #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10
  279. #define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9)
  280. #define SSP_DLL_CTRL_GATE_UPDATE (1 << 7)
  281. #define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3)
  282. #define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3
  283. #define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2)
  284. #define SSP_DLL_CTRL_RESET (1 << 1)
  285. #define SSP_DLL_CTRL_ENABLE (1 << 0)
  286. #define SSP_STATUS_PRESENT (1 << 31)
  287. #define SSP_STATUS_MS_PRESENT (1 << 30)
  288. #define SSP_STATUS_SD_PRESENT (1 << 29)
  289. #define SSP_STATUS_CARD_DETECT (1 << 28)
  290. #define SSP_STATUS_DMABURST (1 << 22)
  291. #define SSP_STATUS_DMASENSE (1 << 21)
  292. #define SSP_STATUS_DMATERM (1 << 20)
  293. #define SSP_STATUS_DMAREQ (1 << 19)
  294. #define SSP_STATUS_DMAEND (1 << 18)
  295. #define SSP_STATUS_SDIO_IRQ (1 << 17)
  296. #define SSP_STATUS_RESP_CRC_ERR (1 << 16)
  297. #define SSP_STATUS_RESP_ERR (1 << 15)
  298. #define SSP_STATUS_RESP_TIMEOUT (1 << 14)
  299. #define SSP_STATUS_DATA_CRC_ERR (1 << 13)
  300. #define SSP_STATUS_TIMEOUT (1 << 12)
  301. #define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11)
  302. #define SSP_STATUS_CEATA_CCS_ERR (1 << 10)
  303. #define SSP_STATUS_FIFO_OVRFLW (1 << 9)
  304. #define SSP_STATUS_FIFO_FULL (1 << 8)
  305. #define SSP_STATUS_FIFO_EMPTY (1 << 5)
  306. #define SSP_STATUS_FIFO_UNDRFLW (1 << 4)
  307. #define SSP_STATUS_CMD_BUSY (1 << 3)
  308. #define SSP_STATUS_DATA_BUSY (1 << 2)
  309. #define SSP_STATUS_BUSY (1 << 0)
  310. #define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8)
  311. #define SSP_DLL_STS_REF_SEL_OFFSET 8
  312. #define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2)
  313. #define SSP_DLL_STS_SLV_SEL_OFFSET 2
  314. #define SSP_DLL_STS_REF_LOCK (1 << 1)
  315. #define SSP_DLL_STS_SLV_LOCK (1 << 0)
  316. #define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28)
  317. #define SSP_DEBUG_DATACRC_ERR_OFFSET 28
  318. #define SSP_DEBUG_DATA_STALL (1 << 27)
  319. #define SSP_DEBUG_DAT_SM_MASK (0x7 << 24)
  320. #define SSP_DEBUG_DAT_SM_OFFSET 24
  321. #define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24)
  322. #define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24)
  323. #define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24)
  324. #define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24)
  325. #define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24)
  326. #define SSP_DEBUG_MSTK_SM_MASK (0xf << 20)
  327. #define SSP_DEBUG_MSTK_SM_OFFSET 20
  328. #define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20)
  329. #define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20)
  330. #define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20)
  331. #define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20)
  332. #define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20)
  333. #define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20)
  334. #define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20)
  335. #define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20)
  336. #define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20)
  337. #define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20)
  338. #define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20)
  339. #define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20)
  340. #define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20)
  341. #define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20)
  342. #define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20)
  343. #define SSP_DEBUG_CMD_OE (1 << 19)
  344. #define SSP_DEBUG_DMA_SM_MASK (0x7 << 16)
  345. #define SSP_DEBUG_DMA_SM_OFFSET 16
  346. #define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16)
  347. #define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16)
  348. #define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16)
  349. #define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16)
  350. #define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16)
  351. #define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16)
  352. #define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16)
  353. #define SSP_DEBUG_MMC_SM_MASK (0xf << 12)
  354. #define SSP_DEBUG_MMC_SM_OFFSET 12
  355. #define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12)
  356. #define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12)
  357. #define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12)
  358. #define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12)
  359. #define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12)
  360. #define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12)
  361. #define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12)
  362. #define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12)
  363. #define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12)
  364. #define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12)
  365. #define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12)
  366. #define SSP_DEBUG_CMD_SM_MASK (0x3 << 10)
  367. #define SSP_DEBUG_CMD_SM_OFFSET 10
  368. #define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10)
  369. #define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10)
  370. #define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10)
  371. #define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10)
  372. #define SSP_DEBUG_SSP_CMD (1 << 9)
  373. #define SSP_DEBUG_SSP_RESP (1 << 8)
  374. #define SSP_DEBUG_SSP_RXD_MASK 0xff
  375. #define SSP_DEBUG_SSP_RXD_OFFSET 0
  376. #define SSP_VERSION_MAJOR_MASK (0xff << 24)
  377. #define SSP_VERSION_MAJOR_OFFSET 24
  378. #define SSP_VERSION_MINOR_MASK (0xff << 16)
  379. #define SSP_VERSION_MINOR_OFFSET 16
  380. #define SSP_VERSION_STEP_MASK 0xffff
  381. #define SSP_VERSION_STEP_OFFSET 0
  382. #endif /* __MX28_REGS_SSP_H__ */