regs-rtc.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 RTC Register Definitions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #ifndef __MX28_REGS_RTC_H__
  9. #define __MX28_REGS_RTC_H__
  10. #include <asm/mach-imx/regs-common.h>
  11. #ifndef __ASSEMBLY__
  12. struct mxs_rtc_regs {
  13. mxs_reg_32(hw_rtc_ctrl)
  14. mxs_reg_32(hw_rtc_stat)
  15. mxs_reg_32(hw_rtc_milliseconds)
  16. mxs_reg_32(hw_rtc_seconds)
  17. mxs_reg_32(hw_rtc_rtc_alarm)
  18. mxs_reg_32(hw_rtc_watchdog)
  19. mxs_reg_32(hw_rtc_persistent0)
  20. mxs_reg_32(hw_rtc_persistent1)
  21. mxs_reg_32(hw_rtc_persistent2)
  22. mxs_reg_32(hw_rtc_persistent3)
  23. mxs_reg_32(hw_rtc_persistent4)
  24. mxs_reg_32(hw_rtc_persistent5)
  25. mxs_reg_32(hw_rtc_debug)
  26. mxs_reg_32(hw_rtc_version)
  27. };
  28. #endif
  29. #define RTC_CTRL_SFTRST (1 << 31)
  30. #define RTC_CTRL_CLKGATE (1 << 30)
  31. #define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6)
  32. #define RTC_CTRL_FORCE_UPDATE (1 << 5)
  33. #define RTC_CTRL_WATCHDOGEN (1 << 4)
  34. #define RTC_CTRL_ONEMSEC_IRQ (1 << 3)
  35. #define RTC_CTRL_ALARM_IRQ (1 << 2)
  36. #define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1)
  37. #define RTC_CTRL_ALARM_IRQ_EN (1 << 0)
  38. #define RTC_STAT_RTC_PRESENT (1 << 31)
  39. #define RTC_STAT_ALARM_PRESENT (1 << 30)
  40. #define RTC_STAT_WATCHDOG_PRESENT (1 << 29)
  41. #define RTC_STAT_XTAL32000_PRESENT (1 << 28)
  42. #define RTC_STAT_XTAL32768_PRESENT (1 << 27)
  43. #define RTC_STAT_STALE_REGS_MASK (0xff << 16)
  44. #define RTC_STAT_STALE_REGS_OFFSET 16
  45. #define RTC_STAT_NEW_REGS_MASK (0xff << 8)
  46. #define RTC_STAT_NEW_REGS_OFFSET 8
  47. #define RTC_MILLISECONDS_COUNT_MASK 0xffffffff
  48. #define RTC_MILLISECONDS_COUNT_OFFSET 0
  49. #define RTC_SECONDS_COUNT_MASK 0xffffffff
  50. #define RTC_SECONDS_COUNT_OFFSET 0
  51. #define RTC_ALARM_VALUE_MASK 0xffffffff
  52. #define RTC_ALARM_VALUE_OFFSET 0
  53. #define RTC_WATCHDOG_COUNT_MASK 0xffffffff
  54. #define RTC_WATCHDOG_COUNT_OFFSET 0
  55. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28)
  56. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28
  57. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28)
  58. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28)
  59. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28)
  60. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28)
  61. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28)
  62. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28)
  63. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28)
  64. #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28)
  65. #define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21)
  66. #define RTC_PERSISTENT0_THERMAL_RESET (1 << 20)
  67. #define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
  68. #define RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
  69. #define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
  70. #define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14)
  71. #define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14
  72. #define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14)
  73. #define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14)
  74. #define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14)
  75. #define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
  76. #define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8)
  77. #define RTC_PERSISTENT0_MSEC_RES_OFFSET 8
  78. #define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8)
  79. #define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8)
  80. #define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8)
  81. #define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8)
  82. #define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8)
  83. #define RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
  84. #define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
  85. #define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
  86. #define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4)
  87. #define RTC_PERSISTENT0_LCK_SECS (1 << 3)
  88. #define RTC_PERSISTENT0_ALARM_EN (1 << 2)
  89. #define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
  90. #define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
  91. #define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff
  92. #define RTC_PERSISTENT1_GENERAL_OFFSET 0
  93. #define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080
  94. #define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100
  95. #define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200
  96. #define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400
  97. #define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800
  98. #define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000
  99. #define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff
  100. #define RTC_PERSISTENT2_GENERAL_OFFSET 0
  101. #define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff
  102. #define RTC_PERSISTENT3_GENERAL_OFFSET 0
  103. #define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff
  104. #define RTC_PERSISTENT4_GENERAL_OFFSET 0
  105. #define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff
  106. #define RTC_PERSISTENT5_GENERAL_OFFSET 0
  107. #define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1)
  108. #define RTC_DEBUG_WATCHDOG_RESET (1 << 0)
  109. #define RTC_VERSION_MAJOR_MASK (0xff << 24)
  110. #define RTC_VERSION_MAJOR_OFFSET 24
  111. #define RTC_VERSION_MINOR_MASK (0xff << 16)
  112. #define RTC_VERSION_MINOR_OFFSET 16
  113. #define RTC_VERSION_STEP_MASK 0xffff
  114. #define RTC_VERSION_STEP_OFFSET 0
  115. #endif /* __MX28_REGS_RTC_H__ */