regs-ocotp.h 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 OCOTP Register Definitions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  10. */
  11. #ifndef __MX28_REGS_OCOTP_H__
  12. #define __MX28_REGS_OCOTP_H__
  13. #include <asm/mach-imx/regs-common.h>
  14. #ifndef __ASSEMBLY__
  15. struct mxs_ocotp_regs {
  16. mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */
  17. mxs_reg_32(hw_ocotp_data) /* 0x10 */
  18. mxs_reg_32(hw_ocotp_cust0) /* 0x20 */
  19. mxs_reg_32(hw_ocotp_cust1) /* 0x30 */
  20. mxs_reg_32(hw_ocotp_cust2) /* 0x40 */
  21. mxs_reg_32(hw_ocotp_cust3) /* 0x50 */
  22. mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */
  23. mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */
  24. mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */
  25. mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */
  26. mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
  27. mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
  28. mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
  29. mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
  30. mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
  31. mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
  32. mxs_reg_32(hw_ocotp_swcap) /* 0x100 */
  33. mxs_reg_32(hw_ocotp_custcap) /* 0x110 */
  34. mxs_reg_32(hw_ocotp_lock) /* 0x120 */
  35. mxs_reg_32(hw_ocotp_ops0) /* 0x130 */
  36. mxs_reg_32(hw_ocotp_ops1) /* 0x140 */
  37. mxs_reg_32(hw_ocotp_ops2) /* 0x150 */
  38. mxs_reg_32(hw_ocotp_ops3) /* 0x160 */
  39. mxs_reg_32(hw_ocotp_un0) /* 0x170 */
  40. mxs_reg_32(hw_ocotp_un1) /* 0x180 */
  41. mxs_reg_32(hw_ocotp_un2) /* 0x190 */
  42. mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */
  43. mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */
  44. mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */
  45. mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */
  46. mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */
  47. mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */
  48. mxs_reg_32(hw_ocotp_rom6) /* 0x200 */
  49. mxs_reg_32(hw_ocotp_rom7) /* 0x210 */
  50. mxs_reg_32(hw_ocotp_srk0) /* 0x220 */
  51. mxs_reg_32(hw_ocotp_srk1) /* 0x230 */
  52. mxs_reg_32(hw_ocotp_srk2) /* 0x240 */
  53. mxs_reg_32(hw_ocotp_srk3) /* 0x250 */
  54. mxs_reg_32(hw_ocotp_srk4) /* 0x260 */
  55. mxs_reg_32(hw_ocotp_srk5) /* 0x270 */
  56. mxs_reg_32(hw_ocotp_srk6) /* 0x280 */
  57. mxs_reg_32(hw_ocotp_srk7) /* 0x290 */
  58. mxs_reg_32(hw_ocotp_version) /* 0x2a0 */
  59. };
  60. #endif
  61. #define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16)
  62. #define OCOTP_CTRL_WR_UNLOCK_OFFSET 16
  63. #define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16)
  64. #define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13)
  65. #define OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
  66. #define OCOTP_CTRL_ERROR (1 << 9)
  67. #define OCOTP_CTRL_BUSY (1 << 8)
  68. #define OCOTP_CTRL_ADDR_MASK 0x3f
  69. #define OCOTP_CTRL_ADDR_OFFSET 0
  70. #define OCOTP_DATA_DATA_MASK 0xffffffff
  71. #define OCOTP_DATA_DATA_OFFSET 0
  72. #define OCOTP_CUST_BITS_MASK 0xffffffff
  73. #define OCOTP_CUST_BITS_OFFSET 0
  74. #define OCOTP_CRYPTO_BITS_MASK 0xffffffff
  75. #define OCOTP_CRYPTO_BITS_OFFSET 0
  76. #define OCOTP_HWCAP_BITS_MASK 0xffffffff
  77. #define OCOTP_HWCAP_BITS_OFFSET 0
  78. #define OCOTP_SWCAP_BITS_MASK 0xffffffff
  79. #define OCOTP_SWCAP_BITS_OFFSET 0
  80. #define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2)
  81. #define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1)
  82. #define OCOTP_LOCK_ROM7 (1 << 31)
  83. #define OCOTP_LOCK_ROM6 (1 << 30)
  84. #define OCOTP_LOCK_ROM5 (1 << 29)
  85. #define OCOTP_LOCK_ROM4 (1 << 28)
  86. #define OCOTP_LOCK_ROM3 (1 << 27)
  87. #define OCOTP_LOCK_ROM2 (1 << 26)
  88. #define OCOTP_LOCK_ROM1 (1 << 25)
  89. #define OCOTP_LOCK_ROM0 (1 << 24)
  90. #define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23)
  91. #define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22)
  92. #define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21)
  93. #define OCOTP_LOCK_PIN (1 << 20)
  94. #define OCOTP_LOCK_OPS (1 << 19)
  95. #define OCOTP_LOCK_UN2 (1 << 18)
  96. #define OCOTP_LOCK_UN1 (1 << 17)
  97. #define OCOTP_LOCK_UN0 (1 << 16)
  98. #define OCOTP_LOCK_SRK (1 << 15)
  99. #define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12)
  100. #define OCOTP_LOCK_UNALLOCATED_OFFSET 12
  101. #define OCOTP_LOCK_SRK_SHADOW (1 << 11)
  102. #define OCOTP_LOCK_ROM_SHADOW (1 << 10)
  103. #define OCOTP_LOCK_CUSTCAP (1 << 9)
  104. #define OCOTP_LOCK_HWSW (1 << 8)
  105. #define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7)
  106. #define OCOTP_LOCK_HWSW_SHADOW (1 << 6)
  107. #define OCOTP_LOCK_CRYPTODCP (1 << 5)
  108. #define OCOTP_LOCK_CRYPTOKEY (1 << 4)
  109. #define OCOTP_LOCK_CUST3 (1 << 3)
  110. #define OCOTP_LOCK_CUST2 (1 << 2)
  111. #define OCOTP_LOCK_CUST1 (1 << 1)
  112. #define OCOTP_LOCK_CUST0 (1 << 0)
  113. #define OCOTP_OPS_BITS_MASK 0xffffffff
  114. #define OCOTP_OPS_BITS_OFFSET 0
  115. #define OCOTP_UN_BITS_MASK 0xffffffff
  116. #define OCOTP_UN_BITS_OFFSET 0
  117. #define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24)
  118. #define OCOTP_ROM_BOOT_MODE_OFFSET 24
  119. #define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22)
  120. #define OCOTP_ROM_SD_MMC_MODE_OFFSET 22
  121. #define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20)
  122. #define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20
  123. #define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14)
  124. #define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14
  125. #define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12)
  126. #define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12
  127. #define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8)
  128. #define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8
  129. #define OCOTP_ROM_EMMC_USE_DDR (1 << 7)
  130. #define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6)
  131. #define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5)
  132. #define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4)
  133. #define OCOTP_ROM_SD_MBR_BOOT (1 << 3)
  134. #define OCOTP_SRK_BITS_MASK 0xffffffff
  135. #define OCOTP_SRK_BITS_OFFSET 0
  136. #define OCOTP_VERSION_MAJOR_MASK (0xff << 24)
  137. #define OCOTP_VERSION_MAJOR_OFFSET 24
  138. #define OCOTP_VERSION_MINOR_MASK (0xff << 16)
  139. #define OCOTP_VERSION_MINOR_OFFSET 16
  140. #define OCOTP_VERSION_STEP_MASK 0xffff
  141. #define OCOTP_VERSION_STEP_OFFSET 0
  142. #endif /* __MX28_REGS_OCOTP_H__ */