regs-digctl.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 DIGCTL Register Definitions
  4. *
  5. * Copyright (C) 2012 Robert Delien <robert@delien.nl>
  6. */
  7. #ifndef __MX28_REGS_DIGCTL_H__
  8. #define __MX28_REGS_DIGCTL_H__
  9. #include <asm/mach-imx/regs-common.h>
  10. #ifndef __ASSEMBLY__
  11. struct mxs_digctl_regs {
  12. mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
  13. mxs_reg_32(hw_digctl_status) /* 0x010 */
  14. mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
  15. mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
  16. mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
  17. mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
  18. uint32_t hw_digctl_writeonce; /* 0x060 */
  19. uint32_t reserved_writeonce[3];
  20. mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
  21. mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
  22. uint32_t hw_digctl_entropy; /* 0x090 */
  23. uint32_t reserved_entropy[3];
  24. uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
  25. uint32_t reserved_entropy_latched[3];
  26. uint32_t reserved1[4];
  27. mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */
  28. uint32_t hw_digctl_dbgrd; /* 0x0d0 */
  29. uint32_t reserved_hw_digctl_dbgrd[3];
  30. uint32_t hw_digctl_dbg; /* 0x0e0 */
  31. uint32_t reserved_hw_digctl_dbg[3];
  32. uint32_t reserved2[4];
  33. mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */
  34. mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */
  35. mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */
  36. mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */
  37. mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */
  38. mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */
  39. mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */
  40. mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */
  41. mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */
  42. mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */
  43. mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
  44. mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
  45. mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
  46. mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
  47. mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
  48. uint32_t reserved3[36];
  49. uint32_t hw_digctl_scratch0; /* 0x280 */
  50. uint32_t reserved_hw_digctl_scratch0[3];
  51. uint32_t hw_digctl_scratch1; /* 0x290 */
  52. uint32_t reserved_hw_digctl_scratch1[3];
  53. uint32_t hw_digctl_armcache; /* 0x2a0 */
  54. uint32_t reserved_hw_digctl_armcache[3];
  55. mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
  56. uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
  57. uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
  58. uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
  59. uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3];
  60. uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */
  61. uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3];
  62. uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */
  63. uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3];
  64. uint32_t hw_digctl_fsl; /* 0x300 */
  65. uint32_t reserved_hw_digctl_fsl[3];
  66. uint32_t hw_digctl_chipid; /* 0x310 */
  67. uint32_t reserved_hw_digctl_chipid[3];
  68. uint32_t reserved4[4];
  69. uint32_t hw_digctl_ahb_stats_select; /* 0x330 */
  70. uint32_t reserved_hw_digctl_ahb_stats_select[3];
  71. uint32_t reserved5[12];
  72. uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */
  73. uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3];
  74. uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */
  75. uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3];
  76. uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */
  77. uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3];
  78. uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */
  79. uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3];
  80. uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */
  81. uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3];
  82. uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */
  83. uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3];
  84. uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */
  85. uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3];
  86. uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */
  87. uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3];
  88. uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */
  89. uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3];
  90. uint32_t reserved6[64];
  91. uint32_t hw_digctl_mpte0_loc; /* 0x500 */
  92. uint32_t reserved_hw_digctl_mpte0_loc[3];
  93. uint32_t hw_digctl_mpte1_loc; /* 0x510 */
  94. uint32_t reserved_hw_digctl_mpte1_loc[3];
  95. uint32_t hw_digctl_mpte2_loc; /* 0x520 */
  96. uint32_t reserved_hw_digctl_mpte2_loc[3];
  97. uint32_t hw_digctl_mpte3_loc; /* 0x530 */
  98. uint32_t reserved_hw_digctl_mpte3_loc[3];
  99. uint32_t hw_digctl_mpte4_loc; /* 0x540 */
  100. uint32_t reserved_hw_digctl_mpte4_loc[3];
  101. uint32_t hw_digctl_mpte5_loc; /* 0x550 */
  102. uint32_t reserved_hw_digctl_mpte5_loc[3];
  103. uint32_t hw_digctl_mpte6_loc; /* 0x560 */
  104. uint32_t reserved_hw_digctl_mpte6_loc[3];
  105. uint32_t hw_digctl_mpte7_loc; /* 0x570 */
  106. uint32_t reserved_hw_digctl_mpte7_loc[3];
  107. uint32_t hw_digctl_mpte8_loc; /* 0x580 */
  108. uint32_t reserved_hw_digctl_mpte8_loc[3];
  109. uint32_t hw_digctl_mpte9_loc; /* 0x590 */
  110. uint32_t reserved_hw_digctl_mpte9_loc[3];
  111. uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */
  112. uint32_t reserved_hw_digctl_mpte10_loc[3];
  113. uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */
  114. uint32_t reserved_hw_digctl_mpte11_loc[3];
  115. uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */
  116. uint32_t reserved_hw_digctl_mpte12_loc[3];
  117. uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */
  118. uint32_t reserved_hw_digctl_mpte13_loc[3];
  119. uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */
  120. uint32_t reserved_hw_digctl_mpte14_loc[3];
  121. uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */
  122. uint32_t reserved_hw_digctl_mpte15_loc[3];
  123. };
  124. #endif
  125. /* Product code identification */
  126. #define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
  127. #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
  128. #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
  129. #endif /* __MX28_REGS_DIGCTL_H__ */