regs-clkctrl-mx28.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 CLKCTRL Register Definitions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  10. */
  11. #ifndef __MX28_REGS_CLKCTRL_H__
  12. #define __MX28_REGS_CLKCTRL_H__
  13. #include <asm/mach-imx/regs-common.h>
  14. #ifndef __ASSEMBLY__
  15. struct mxs_clkctrl_regs {
  16. mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
  17. uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
  18. uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
  19. mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
  20. uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */
  21. uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
  22. mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
  23. mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
  24. mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
  25. mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
  26. mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
  27. uint32_t hw_clkctrl_ssp0; /* 0x90 */
  28. uint32_t reserved_ssp0[3]; /* 0x94-0x9c */
  29. uint32_t hw_clkctrl_ssp1; /* 0xa0 */
  30. uint32_t reserved_ssp1[3]; /* 0xa4-0xac */
  31. uint32_t hw_clkctrl_ssp2; /* 0xb0 */
  32. uint32_t reserved_ssp2[3]; /* 0xb4-0xbc */
  33. uint32_t hw_clkctrl_ssp3; /* 0xc0 */
  34. uint32_t reserved_ssp3[3]; /* 0xc4-0xcc */
  35. uint32_t hw_clkctrl_gpmi; /* 0xd0 */
  36. uint32_t reserved_gpmi[3]; /* 0xd4-0xdc */
  37. mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
  38. mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
  39. mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
  40. mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */
  41. mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */
  42. mxs_reg_32(hw_clkctrl_etm) /* 0x130 */
  43. mxs_reg_32(hw_clkctrl_enet) /* 0x140 */
  44. mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */
  45. mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */
  46. uint32_t reserved[16];
  47. mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
  48. mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
  49. mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
  50. mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */
  51. mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */
  52. mxs_reg_32(hw_clkctrl_version) /* 0x200 */
  53. };
  54. #endif
  55. #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
  56. #define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
  57. #define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
  58. #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
  59. #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
  60. #define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
  61. #define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
  62. #define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
  63. #define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
  64. #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
  65. #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
  66. #define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
  67. #define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
  68. #define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
  69. #define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
  70. #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
  71. #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
  72. #define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
  73. #define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
  74. #define CLKCTRL_PLL0CTRL0_POWER (1 << 17)
  75. #define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
  76. #define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
  77. #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
  78. #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
  79. #define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31)
  80. #define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28)
  81. #define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28
  82. #define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
  83. #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
  84. #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
  85. #define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
  86. #define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24)
  87. #define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24
  88. #define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24)
  89. #define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
  90. #define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
  91. #define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
  92. #define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20)
  93. #define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20
  94. #define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
  95. #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20)
  96. #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20)
  97. #define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
  98. #define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18)
  99. #define CLKCTRL_PLL1CTRL0_POWER (1 << 17)
  100. #define CLKCTRL_PLL1CTRL1_LOCK (1 << 31)
  101. #define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30)
  102. #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff
  103. #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0
  104. #define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31)
  105. #define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28)
  106. #define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28
  107. #define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26)
  108. #define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24)
  109. #define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24
  110. #define CLKCTRL_PLL2CTRL0_POWER (1 << 23)
  111. #define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
  112. #define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
  113. #define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
  114. #define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
  115. #define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
  116. #define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
  117. #define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
  118. #define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
  119. #define CLKCTRL_CPU_DIV_CPU_OFFSET 0
  120. #define CLKCTRL_HBUS_ASM_BUSY (1 << 31)
  121. #define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30)
  122. #define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29)
  123. #define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27)
  124. #define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
  125. #define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
  126. #define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
  127. #define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
  128. #define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
  129. #define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
  130. #define CLKCTRL_HBUS_ASM_ENABLE (1 << 20)
  131. #define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19)
  132. #define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
  133. #define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
  134. #define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
  135. #define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
  136. #define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
  137. #define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
  138. #define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
  139. #define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
  140. #define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
  141. #define CLKCTRL_HBUS_DIV_MASK 0x1f
  142. #define CLKCTRL_HBUS_DIV_OFFSET 0
  143. #define CLKCTRL_XBUS_BUSY (1 << 31)
  144. #define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11)
  145. #define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
  146. #define CLKCTRL_XBUS_DIV_MASK 0x3ff
  147. #define CLKCTRL_XBUS_DIV_OFFSET 0
  148. #define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
  149. #define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
  150. #define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
  151. #define CLKCTRL_XTAL_DIV_UART_MASK 0x3
  152. #define CLKCTRL_XTAL_DIV_UART_OFFSET 0
  153. #define CLKCTRL_SSP_CLKGATE (1 << 31)
  154. #define CLKCTRL_SSP_BUSY (1 << 29)
  155. #define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
  156. #define CLKCTRL_SSP_DIV_MASK 0x1ff
  157. #define CLKCTRL_SSP_DIV_OFFSET 0
  158. #define CLKCTRL_GPMI_CLKGATE (1 << 31)
  159. #define CLKCTRL_GPMI_BUSY (1 << 29)
  160. #define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
  161. #define CLKCTRL_GPMI_DIV_MASK 0x3ff
  162. #define CLKCTRL_GPMI_DIV_OFFSET 0
  163. #define CLKCTRL_SPDIF_CLKGATE (1 << 31)
  164. #define CLKCTRL_EMI_CLKGATE (1 << 31)
  165. #define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
  166. #define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
  167. #define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
  168. #define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
  169. #define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
  170. #define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
  171. #define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
  172. #define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
  173. #define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
  174. #define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
  175. #define CLKCTRL_EMI_DIV_EMI_OFFSET 0
  176. #define CLKCTRL_SAIF0_CLKGATE (1 << 31)
  177. #define CLKCTRL_SAIF0_BUSY (1 << 29)
  178. #define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
  179. #define CLKCTRL_SAIF0_DIV_MASK 0xffff
  180. #define CLKCTRL_SAIF0_DIV_OFFSET 0
  181. #define CLKCTRL_SAIF1_CLKGATE (1 << 31)
  182. #define CLKCTRL_SAIF1_BUSY (1 << 29)
  183. #define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16)
  184. #define CLKCTRL_SAIF1_DIV_MASK 0xffff
  185. #define CLKCTRL_SAIF1_DIV_OFFSET 0
  186. #define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31)
  187. #define CLKCTRL_DIS_LCDIF_BUSY (1 << 29)
  188. #define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13)
  189. #define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff
  190. #define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0
  191. #define CLKCTRL_ETM_CLKGATE (1 << 31)
  192. #define CLKCTRL_ETM_BUSY (1 << 29)
  193. #define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7)
  194. #define CLKCTRL_ETM_DIV_MASK 0x7f
  195. #define CLKCTRL_ETM_DIV_OFFSET 0
  196. #define CLKCTRL_ENET_SLEEP (1 << 31)
  197. #define CLKCTRL_ENET_DISABLE (1 << 30)
  198. #define CLKCTRL_ENET_STATUS (1 << 29)
  199. #define CLKCTRL_ENET_BUSY_TIME (1 << 27)
  200. #define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21)
  201. #define CLKCTRL_ENET_DIV_TIME_OFFSET 21
  202. #define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19)
  203. #define CLKCTRL_ENET_TIME_SEL_OFFSET 19
  204. #define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19)
  205. #define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19)
  206. #define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19)
  207. #define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19)
  208. #define CLKCTRL_ENET_CLK_OUT_EN (1 << 18)
  209. #define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17)
  210. #define CLKCTRL_ENET_RESET_BY_SW (1 << 16)
  211. #define CLKCTRL_HSADC_RESETB (1 << 30)
  212. #define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28)
  213. #define CLKCTRL_HSADC_FREQDIV_OFFSET 28
  214. #define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30)
  215. #define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29)
  216. #define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)
  217. #define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27)
  218. #define CLKCTRL_FRAC_CLKGATE (1 << 7)
  219. #define CLKCTRL_FRAC_STABLE (1 << 6)
  220. #define CLKCTRL_FRAC_FRAC_MASK 0x3f
  221. #define CLKCTRL_FRAC_FRAC_OFFSET 0
  222. #define CLKCTRL_FRAC0_CPU 0
  223. #define CLKCTRL_FRAC0_EMI 1
  224. #define CLKCTRL_FRAC0_IO1 2
  225. #define CLKCTRL_FRAC0_IO0 3
  226. #define CLKCTRL_FRAC1_PIX 0
  227. #define CLKCTRL_FRAC1_HSADC 1
  228. #define CLKCTRL_FRAC1_GPMI 2
  229. #define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
  230. #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
  231. #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14)
  232. #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14)
  233. #define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
  234. #define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7)
  235. #define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6)
  236. #define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5)
  237. #define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4)
  238. #define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3)
  239. #define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2)
  240. #define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1)
  241. #define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0)
  242. #define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5)
  243. #define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4)
  244. #define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3)
  245. #define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2)
  246. #define CLKCTRL_RESET_CHIP (1 << 1)
  247. #define CLKCTRL_RESET_DIG (1 << 0)
  248. #define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
  249. #define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
  250. #define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
  251. #define CLKCTRL_VERSION_MAJOR_OFFSET 24
  252. #define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
  253. #define CLKCTRL_VERSION_MINOR_OFFSET 16
  254. #define CLKCTRL_VERSION_STEP_MASK 0xffff
  255. #define CLKCTRL_VERSION_STEP_OFFSET 0
  256. #endif /* __MX28_REGS_CLKCTRL_H__ */