regs-clkctrl-mx23.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX23 CLKCTRL Register Definitions
  4. *
  5. * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  10. */
  11. #ifndef __MX23_REGS_CLKCTRL_H__
  12. #define __MX23_REGS_CLKCTRL_H__
  13. #include <asm/mach-imx/regs-common.h>
  14. #ifndef __ASSEMBLY__
  15. struct mxs_clkctrl_regs {
  16. mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
  17. uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
  18. uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
  19. mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */
  20. mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */
  21. mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
  22. mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
  23. mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
  24. uint32_t hw_clkctrl_ssp0; /* 0x70 */
  25. uint32_t reserved_ssp0[3]; /* 0x74-0x7c */
  26. uint32_t hw_clkctrl_gpmi; /* 0x80 */
  27. uint32_t reserved_gpmi[3]; /* 0x84-0x8c */
  28. mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
  29. mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */
  30. uint32_t reserved1[4];
  31. mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */
  32. mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */
  33. mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */
  34. mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */
  35. mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
  36. mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */
  37. mxs_reg_32(hw_clkctrl_reset) /* 0x120 */
  38. mxs_reg_32(hw_clkctrl_status) /* 0x130 */
  39. mxs_reg_32(hw_clkctrl_version) /* 0x140 */
  40. };
  41. #endif
  42. #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
  43. #define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
  44. #define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
  45. #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
  46. #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
  47. #define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
  48. #define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
  49. #define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
  50. #define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
  51. #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
  52. #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
  53. #define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
  54. #define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
  55. #define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
  56. #define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
  57. #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
  58. #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
  59. #define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
  60. #define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
  61. #define CLKCTRL_PLL0CTRL0_POWER (1 << 16)
  62. #define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
  63. #define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
  64. #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
  65. #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
  66. #define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
  67. #define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
  68. #define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
  69. #define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
  70. #define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
  71. #define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
  72. #define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
  73. #define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
  74. #define CLKCTRL_CPU_DIV_CPU_OFFSET 0
  75. #define CLKCTRL_HBUS_BUSY (1 << 29)
  76. #define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28)
  77. #define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27)
  78. #define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
  79. #define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
  80. #define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
  81. #define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
  82. #define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
  83. #define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
  84. #define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20)
  85. #define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
  86. #define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
  87. #define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
  88. #define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
  89. #define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
  90. #define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
  91. #define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
  92. #define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
  93. #define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
  94. #define CLKCTRL_HBUS_DIV_MASK 0x1f
  95. #define CLKCTRL_HBUS_DIV_OFFSET 0
  96. #define CLKCTRL_XBUS_BUSY (1 << 31)
  97. #define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
  98. #define CLKCTRL_XBUS_DIV_MASK 0x3ff
  99. #define CLKCTRL_XBUS_DIV_OFFSET 0
  100. #define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
  101. #define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30)
  102. #define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
  103. #define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28)
  104. #define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27)
  105. #define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
  106. #define CLKCTRL_XTAL_DIV_UART_MASK 0x3
  107. #define CLKCTRL_XTAL_DIV_UART_OFFSET 0
  108. #define CLKCTRL_PIX_CLKGATE (1 << 31)
  109. #define CLKCTRL_PIX_BUSY (1 << 29)
  110. #define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12)
  111. #define CLKCTRL_PIX_DIV_MASK 0xfff
  112. #define CLKCTRL_PIX_DIV_OFFSET 0
  113. #define CLKCTRL_SSP_CLKGATE (1 << 31)
  114. #define CLKCTRL_SSP_BUSY (1 << 29)
  115. #define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
  116. #define CLKCTRL_SSP_DIV_MASK 0x1ff
  117. #define CLKCTRL_SSP_DIV_OFFSET 0
  118. #define CLKCTRL_GPMI_CLKGATE (1 << 31)
  119. #define CLKCTRL_GPMI_BUSY (1 << 29)
  120. #define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
  121. #define CLKCTRL_GPMI_DIV_MASK 0x3ff
  122. #define CLKCTRL_GPMI_DIV_OFFSET 0
  123. #define CLKCTRL_SPDIF_CLKGATE (1 << 31)
  124. #define CLKCTRL_EMI_CLKGATE (1 << 31)
  125. #define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
  126. #define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
  127. #define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
  128. #define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
  129. #define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
  130. #define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
  131. #define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
  132. #define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
  133. #define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
  134. #define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
  135. #define CLKCTRL_EMI_DIV_EMI_OFFSET 0
  136. #define CLKCTRL_IR_CLKGATE (1 << 31)
  137. #define CLKCTRL_IR_AUTO_DIV (1 << 29)
  138. #define CLKCTRL_IR_IR_BUSY (1 << 28)
  139. #define CLKCTRL_IR_IROV_BUSY (1 << 27)
  140. #define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16)
  141. #define CLKCTRL_IR_IROV_DIV_OFFSET 16
  142. #define CLKCTRL_IR_IR_DIV_MASK 0x3ff
  143. #define CLKCTRL_IR_IR_DIV_OFFSET 0
  144. #define CLKCTRL_SAIF0_CLKGATE (1 << 31)
  145. #define CLKCTRL_SAIF0_BUSY (1 << 29)
  146. #define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
  147. #define CLKCTRL_SAIF0_DIV_MASK 0xffff
  148. #define CLKCTRL_SAIF0_DIV_OFFSET 0
  149. #define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31)
  150. #define CLKCTRL_TV_CLK_TV_GATE (1 << 30)
  151. #define CLKCTRL_ETM_CLKGATE (1 << 31)
  152. #define CLKCTRL_ETM_BUSY (1 << 29)
  153. #define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6)
  154. #define CLKCTRL_ETM_DIV_MASK 0x3f
  155. #define CLKCTRL_ETM_DIV_OFFSET 0
  156. #define CLKCTRL_FRAC_CLKGATE (1 << 7)
  157. #define CLKCTRL_FRAC_STABLE (1 << 6)
  158. #define CLKCTRL_FRAC_FRAC_MASK 0x3f
  159. #define CLKCTRL_FRAC_FRAC_OFFSET 0
  160. #define CLKCTRL_FRAC0_CPU 0
  161. #define CLKCTRL_FRAC0_EMI 1
  162. #define CLKCTRL_FRAC0_PIX 2
  163. #define CLKCTRL_FRAC0_IO0 3
  164. #define CLKCTRL_FRAC1_VID 3
  165. #define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
  166. #define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
  167. #define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
  168. #define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5)
  169. #define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
  170. #define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3)
  171. #define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1)
  172. #define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0)
  173. #define CLKCTRL_RESET_CHIP (1 << 1)
  174. #define CLKCTRL_RESET_DIG (1 << 0)
  175. #define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
  176. #define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
  177. #define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
  178. #define CLKCTRL_VERSION_MAJOR_OFFSET 24
  179. #define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
  180. #define CLKCTRL_VERSION_MINOR_OFFSET 16
  181. #define CLKCTRL_VERSION_STEP_MASK 0xffff
  182. #define CLKCTRL_VERSION_STEP_OFFSET 0
  183. #endif /* __MX23_REGS_CLKCTRL_H__ */