mx6sx_rdc.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __MX6SX_RDC_H__
  6. #define __MX6SX_RDC_H__
  7. #define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */
  8. enum {
  9. RDC_PER_PWM1 = 0,
  10. RDC_PER_PWM2,
  11. RDC_PER_PWM3,
  12. RDC_PER_PWM4,
  13. RDC_PER_CAN1,
  14. RDC_PER_CAN2,
  15. RDC_PER_GPT,
  16. RDC_PER_GPIO1,
  17. RDC_PER_GPIO2,
  18. RDC_PER_GPIO3,
  19. RDC_PER_GPIO4,
  20. RDC_PER_GPIO5,
  21. RDC_PER_GPIO6,
  22. RDC_PER_GPIO7,
  23. RDC_PER_KPP,
  24. RDC_PER_WDOG1,
  25. RDC_PER_WODG2,
  26. RDC_PER_CCM,
  27. RDC_PER_ANATOPDIG,
  28. RDC_PER_SNVSHP,
  29. RDC_PER_EPIT1,
  30. RDC_PER_EPIT2,
  31. RDC_PER_SRC,
  32. RDC_PER_GPC,
  33. RDC_PER_IOMUXC,
  34. RDC_PER_IOMUXCGPR,
  35. RDC_PER_CANFD1,
  36. RDC_PER_SDMA,
  37. RDC_PER_CANFD2,
  38. RDC_PER_SEMA1,
  39. RDC_PER_SEMA2,
  40. RDC_PER_RDC,
  41. RDC_PER_AIPSTZ1_GE1,
  42. RDC_PER_AIPSTZ2_GE2,
  43. RDC_PER_USBO2H_PL301,
  44. RDC_PER_USBO2H_USB,
  45. RDC_PER_ENET1,
  46. RDC_PER_MLB25,
  47. RDC_PER_USDHC1,
  48. RDC_PER_USDHC2,
  49. RDC_PER_USDHC3,
  50. RDC_PER_USDHC4,
  51. RDC_PER_I2C1,
  52. RDC_PER_I2C2,
  53. RDC_PER_I2C3,
  54. RDC_PER_ROMCP,
  55. RDC_PER_MMDC,
  56. RDC_PER_ENET2,
  57. RDC_PER_EIM,
  58. RDC_PER_OCOTP,
  59. RDC_PER_CSU,
  60. RDC_PER_PERFMON1,
  61. RDC_PER_PERFMON2,
  62. RDC_PER_AXIMON,
  63. RDC_PER_TZASC1,
  64. RDC_PER_SAI1,
  65. RDC_PER_AUDMUX,
  66. RDC_PER_SAI2,
  67. RDC_PER_QSPI1,
  68. RDC_PER_QSPI2,
  69. RDC_PER_UART2,
  70. RDC_PER_UART3,
  71. RDC_PER_UART4,
  72. RDC_PER_UART5,
  73. RDC_PER_I2C4,
  74. RDC_PER_QOSC,
  75. RDC_PER_CAAM,
  76. RDC_PER_DAP,
  77. RDC_PER_ADC1,
  78. RDC_PER_ADC2,
  79. RDC_PER_WDOG3,
  80. RDC_PER_ECSPI5,
  81. RDC_PER_SEMA4,
  82. RDC_PER_MUPORT1,
  83. RDC_PER_CANFD_CPU,
  84. RDC_PER_MUPORT2,
  85. RDC_PER_UART6,
  86. RDC_PER_PWM5,
  87. RDC_PER_PWM6,
  88. RDC_PER_PWM7,
  89. RDC_PER_PWM8,
  90. RDC_PER_AIPSTZ3_GE0,
  91. RDC_PER_AIPSTZ3_GE1,
  92. RDC_PER_RESERVED1,
  93. RDC_PER_SPDIF,
  94. RDC_PER_ECSPI1,
  95. RDC_PER_ECSPI2,
  96. RDC_PER_ECSPI3,
  97. RDC_PER_ECSPI4,
  98. RDC_PER_RESERVED2,
  99. RDC_PER_RESERVED3,
  100. RDC_PER_UART1,
  101. RDC_PER_ESAI,
  102. RDC_PER_SSI1,
  103. RDC_PER_SSI2,
  104. RDC_PER_SSI3,
  105. RDC_PER_ASRC,
  106. RDC_PER_RESERVED4,
  107. RDC_PER_SPBA_MA,
  108. RDC_PER_GIS,
  109. RDC_PER_DCIC1,
  110. RDC_PER_DCIC2,
  111. RDC_PER_CSI1,
  112. RDC_PER_PXP,
  113. RDC_PER_CSI2,
  114. RDC_PER_LCDIF1,
  115. RDC_PER_LCDIF2,
  116. RDC_PER_VADC,
  117. RDC_PER_VDEC,
  118. RDC_PER_SPBA_DISPLAYMIX,
  119. };
  120. enum {
  121. RDC_MA_A9_L2CACHE = 0,
  122. RDC_MA_M4,
  123. RDC_MA_GPU,
  124. RDC_MA_CSI1,
  125. RDC_MA_CSI2,
  126. RDC_MA_LCDIF1,
  127. RDC_MA_LCDIF2,
  128. RDC_MA_PXP,
  129. RDC_MA_PCIE_CTRL,
  130. RDC_MA_DAP,
  131. RDC_MA_CAAM,
  132. RDC_MA_SDMA_PERI,
  133. RDC_MA_SDMA_BURST,
  134. RDC_MA_APBHDMA,
  135. RDC_MA_RAWNAND,
  136. RDC_MA_USDHC1,
  137. RDC_MA_USDHC2,
  138. RDC_MA_USDHC3,
  139. RDC_MA_USDHC4,
  140. RDC_MA_USB,
  141. RDC_MA_MLB,
  142. RDC_MA_TEST,
  143. RDC_MA_ENET1_TX,
  144. RDC_MA_ENET1_RX,
  145. RDC_MA_ENET2_TX,
  146. RDC_MA_ENET2_RX,
  147. RDC_MA_SDMA,
  148. };
  149. #endif /* __MX6SX_RDC_H__*/