mx6sl-ddr.h 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ASM_ARCH_MX6SL_DDR_H__
  6. #define __ASM_ARCH_MX6SL_DDR_H__
  7. #ifndef CONFIG_MX6SL
  8. #error "wrong CPU"
  9. #endif
  10. #define MX6_IOM_DRAM_CAS_B 0x020e0300
  11. #define MX6_IOM_DRAM_CS0_B 0x020e0304
  12. #define MX6_IOM_DRAM_CS1_B 0x020e0308
  13. #define MX6_IOM_DRAM_DQM0 0x020e030c
  14. #define MX6_IOM_DRAM_DQM1 0x020e0310
  15. #define MX6_IOM_DRAM_DQM2 0x020e0314
  16. #define MX6_IOM_DRAM_DQM3 0x020e0318
  17. #define MX6_IOM_DRAM_RAS_B 0x020e031c
  18. #define MX6_IOM_DRAM_RESET 0x020e0320
  19. #define MX6_IOM_DRAM_SDBA0 0x020e0324
  20. #define MX6_IOM_DRAM_SDBA1 0x020e0328
  21. #define MX6_IOM_DRAM_SDBA2 0x020e032c
  22. #define MX6_IOM_DRAM_SDCKE0 0x020e0330
  23. #define MX6_IOM_DRAM_SDCKE1 0x020e0334
  24. #define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
  25. #define MX6_IOM_DRAM_ODT0 0x020e033c
  26. #define MX6_IOM_DRAM_ODT1 0x020e0340
  27. #define MX6_IOM_DRAM_SDQS0_P 0x020e0344
  28. #define MX6_IOM_DRAM_SDQS1_P 0x020e0348
  29. #define MX6_IOM_DRAM_SDQS2_P 0x020e034c
  30. #define MX6_IOM_DRAM_SDQS3_P 0x020e0350
  31. #define MX6_IOM_DRAM_SDWE_B 0x020e0354
  32. #endif /*__ASM_ARCH_MX6SL_DDR_H__ */