iomux.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #ifndef __ASM_ARCH_IOMUX_H__
  3. #define __ASM_ARCH_IOMUX_H__
  4. #define MX6_IOMUXC_GPR4 0x020e0010
  5. #define MX6_IOMUXC_GPR6 0x020e0018
  6. #define MX6_IOMUXC_GPR7 0x020e001c
  7. /*
  8. * IOMUXC_GPR1 bit fields
  9. */
  10. #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13)
  11. #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13)
  12. #define IOMUXC_GPR1_OTG_ID_MASK (1<<13)
  13. #define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
  14. #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
  15. #define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
  16. /*
  17. * IOMUXC_GPR5 bit fields
  18. */
  19. #define IOMUXC_GPR5_PCIE_BTNRST (1 << 19)
  20. #define IOMUXC_GPR5_PCIE_PERST (1 << 18)
  21. /*
  22. * IOMUXC_GPR8 bit fields
  23. */
  24. #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0)
  25. #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0
  26. #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6)
  27. #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6
  28. #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12)
  29. #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12
  30. #define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18)
  31. #define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18
  32. #define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25)
  33. #define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25
  34. /*
  35. * IOMUXC_GPR12 bit fields
  36. */
  37. #define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0)
  38. #define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0)
  39. #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4)
  40. #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
  41. #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
  42. #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
  43. #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
  44. #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
  45. #define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30)
  46. /*
  47. * IOMUXC_GPR13 bit fields
  48. */
  49. #define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30)
  50. #define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29)
  51. #define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28)
  52. #define IOMUXC_GPR13_ENET_STOP_REQ (1<<27)
  53. #define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24)
  54. #define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19)
  55. #define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
  56. #define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  57. #define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15)
  58. #define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14)
  59. #define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11)
  60. #define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7)
  61. #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
  62. #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
  63. #define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
  64. #define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
  65. #define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
  66. | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
  67. #define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
  68. #define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
  69. #define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
  70. | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
  71. #define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
  72. #define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
  73. #define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
  74. | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
  75. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
  76. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
  77. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
  78. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24)
  79. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24)
  80. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24)
  81. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24)
  82. #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24)
  83. #define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19)
  84. #define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19)
  85. #define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19)
  86. #define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19)
  87. #define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19)
  88. #define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19)
  89. #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
  90. #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
  91. #define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14)
  92. #define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14)
  93. #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11)
  94. #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11)
  95. #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11)
  96. #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11)
  97. #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
  98. #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
  99. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7)
  100. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7)
  101. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7)
  102. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7)
  103. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7)
  104. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7)
  105. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7)
  106. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7)
  107. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7)
  108. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7)
  109. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7)
  110. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7)
  111. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7)
  112. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7)
  113. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7)
  114. #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7)
  115. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2)
  116. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2)
  117. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2)
  118. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2)
  119. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2)
  120. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2)
  121. #define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2)
  122. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2)
  123. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2)
  124. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2)
  125. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2)
  126. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2)
  127. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2)
  128. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2)
  129. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2)
  130. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2)
  131. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2)
  132. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2)
  133. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2)
  134. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2)
  135. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2)
  136. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2)
  137. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2)
  138. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2)
  139. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2)
  140. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2)
  141. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2)
  142. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2)
  143. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2)
  144. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2)
  145. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2)
  146. #define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2)
  147. #define IOMUXC_GPR13_SATA_PHY_1_FAST 0
  148. #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
  149. #define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
  150. #define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
  151. |IOMUXC_GPR13_SATA_PHY_7_MASK \
  152. |IOMUXC_GPR13_SATA_PHY_6_MASK \
  153. |IOMUXC_GPR13_SATA_SPEED_MASK \
  154. |IOMUXC_GPR13_SATA_PHY_5_MASK \
  155. |IOMUXC_GPR13_SATA_PHY_4_MASK \
  156. |IOMUXC_GPR13_SATA_PHY_3_MASK \
  157. |IOMUXC_GPR13_SATA_PHY_2_MASK \
  158. |IOMUXC_GPR13_SATA_PHY_1_MASK)
  159. /*
  160. * Setup RGMII voltage levels on iMX6 SoC - the
  161. *
  162. * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register
  163. *
  164. * 1P2V_IO - USB_HSIC, MIPI_HSI
  165. * 1P5V_IO - ENET pins
  166. */
  167. #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x020e0790
  168. #define DDR_SEL_1P2V_IO (0x2 << 18)
  169. #define DDR_SEL_1P5V_IO (0x3 << 18)
  170. #endif /* __ASM_ARCH_IOMUX_H__ */