imx-regs.h 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  4. */
  5. #ifndef __ASM_ARCH_MX31_IMX_REGS_H
  6. #define __ASM_ARCH_MX31_IMX_REGS_H
  7. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  8. #include <asm/types.h>
  9. /* Clock control module registers */
  10. struct clock_control_regs {
  11. u32 ccmr;
  12. u32 pdr0;
  13. u32 pdr1;
  14. u32 rcsr;
  15. u32 mpctl;
  16. u32 upctl;
  17. u32 spctl;
  18. u32 cosr;
  19. u32 cgr0;
  20. u32 cgr1;
  21. u32 cgr2;
  22. u32 wimr0;
  23. u32 ldc;
  24. u32 dcvr0;
  25. u32 dcvr1;
  26. u32 dcvr2;
  27. u32 dcvr3;
  28. u32 ltr0;
  29. u32 ltr1;
  30. u32 ltr2;
  31. u32 ltr3;
  32. u32 ltbr0;
  33. u32 ltbr1;
  34. u32 pmcr0;
  35. u32 pmcr1;
  36. u32 pdr2;
  37. };
  38. struct cspi_regs {
  39. u32 rxdata;
  40. u32 txdata;
  41. u32 ctrl;
  42. u32 intr;
  43. u32 dma;
  44. u32 stat;
  45. u32 period;
  46. u32 test;
  47. };
  48. /* IIM control registers */
  49. struct iim_regs {
  50. u32 iim_stat;
  51. u32 iim_statm;
  52. u32 iim_err;
  53. u32 iim_emask;
  54. u32 iim_fctl;
  55. u32 iim_ua;
  56. u32 iim_la;
  57. u32 iim_sdat;
  58. u32 iim_prev;
  59. u32 iim_srev;
  60. u32 iim_prg_p;
  61. u32 iim_scs0;
  62. u32 iim_scs1;
  63. u32 iim_scs2;
  64. u32 iim_scs3;
  65. u32 res[0x1f1];
  66. struct fuse_bank {
  67. u32 fuse_regs[0x20];
  68. u32 fuse_rsvd[0xe0];
  69. } bank[3];
  70. };
  71. struct fuse_bank0_regs {
  72. u32 fuse0_5[6];
  73. u32 usr;
  74. u32 fuse7_15[9];
  75. };
  76. struct fuse_bank2_regs {
  77. u32 fuse0;
  78. u32 uid[8];
  79. u32 fuse9_15[7];
  80. };
  81. struct iomuxc_regs {
  82. u32 unused1;
  83. u32 unused2;
  84. u32 gpr;
  85. };
  86. struct mx3_cpu_type {
  87. u8 srev;
  88. u32 v;
  89. };
  90. #define IOMUX_PADNUM_MASK 0x1ff
  91. #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
  92. /*
  93. * various IOMUX pad functions
  94. */
  95. enum iomux_pad_config {
  96. PAD_CTL_NOLOOPBACK = 0x0 << 9,
  97. PAD_CTL_LOOPBACK = 0x1 << 9,
  98. PAD_CTL_PKE_NONE = 0x0 << 8,
  99. PAD_CTL_PKE_ENABLE = 0x1 << 8,
  100. PAD_CTL_PUE_KEEPER = 0x0 << 7,
  101. PAD_CTL_PUE_PUD = 0x1 << 7,
  102. PAD_CTL_100K_PD = 0x0 << 5,
  103. PAD_CTL_100K_PU = 0x1 << 5,
  104. PAD_CTL_47K_PU = 0x2 << 5,
  105. PAD_CTL_22K_PU = 0x3 << 5,
  106. PAD_CTL_HYS_CMOS = 0x0 << 4,
  107. PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
  108. PAD_CTL_ODE_CMOS = 0x0 << 3,
  109. PAD_CTL_ODE_OpenDrain = 0x1 << 3,
  110. PAD_CTL_DRV_NORMAL = 0x0 << 1,
  111. PAD_CTL_DRV_HIGH = 0x1 << 1,
  112. PAD_CTL_DRV_MAX = 0x2 << 1,
  113. PAD_CTL_SRE_SLOW = 0x0 << 0,
  114. PAD_CTL_SRE_FAST = 0x1 << 0
  115. };
  116. /*
  117. * This enumeration is constructed based on the Section
  118. * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
  119. * value is constructed based on the rules described above.
  120. */
  121. enum iomux_pins {
  122. MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
  123. MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
  124. MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
  125. MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
  126. MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
  127. MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
  128. MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
  129. MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
  130. MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
  131. MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
  132. MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
  133. MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
  134. MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
  135. MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
  136. MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
  137. MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
  138. MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
  139. MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
  140. MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
  141. MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
  142. MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
  143. MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
  144. MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
  145. MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
  146. MX31_PIN_READ = IOMUX_PIN(0xff, 24),
  147. MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
  148. MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
  149. MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
  150. MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
  151. MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
  152. MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
  153. MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
  154. MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
  155. MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
  156. MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
  157. MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
  158. MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
  159. MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
  160. MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
  161. MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
  162. MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
  163. MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
  164. MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
  165. MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
  166. MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
  167. MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
  168. MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
  169. MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
  170. MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
  171. MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
  172. MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
  173. MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
  174. MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
  175. MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
  176. MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
  177. MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
  178. MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
  179. MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
  180. MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
  181. MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
  182. MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
  183. MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
  184. MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
  185. MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
  186. MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
  187. MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
  188. MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
  189. MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
  190. MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
  191. MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
  192. MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
  193. MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
  194. MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
  195. MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
  196. MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
  197. MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
  198. MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
  199. MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
  200. MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
  201. MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
  202. MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
  203. MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
  204. MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
  205. MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
  206. MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
  207. MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
  208. MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
  209. MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
  210. MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
  211. MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
  212. MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
  213. MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
  214. MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
  215. MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
  216. MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
  217. MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
  218. MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
  219. MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
  220. MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
  221. MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
  222. MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
  223. MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
  224. MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
  225. MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
  226. MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
  227. MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
  228. MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
  229. MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
  230. MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
  231. MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
  232. MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
  233. MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
  234. MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
  235. MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
  236. MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
  237. MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
  238. MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
  239. MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
  240. MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
  241. MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
  242. MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
  243. MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
  244. MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
  245. MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
  246. MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
  247. MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
  248. MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
  249. MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
  250. MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
  251. MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
  252. MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
  253. MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
  254. MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
  255. MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
  256. MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
  257. MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
  258. MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
  259. MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
  260. MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
  261. MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
  262. MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
  263. MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
  264. MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
  265. MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
  266. MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
  267. MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
  268. MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
  269. MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
  270. MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
  271. MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
  272. MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
  273. MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
  274. MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
  275. MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
  276. MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
  277. MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
  278. MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
  279. MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
  280. MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
  281. MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
  282. MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
  283. MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
  284. MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
  285. MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
  286. MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
  287. MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
  288. MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
  289. MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
  290. MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
  291. MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
  292. MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
  293. MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
  294. MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
  295. MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
  296. MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
  297. MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
  298. MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
  299. MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
  300. MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
  301. MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
  302. MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
  303. MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
  304. MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
  305. MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
  306. MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
  307. MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
  308. MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
  309. MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
  310. MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
  311. MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
  312. MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
  313. MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
  314. MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
  315. MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
  316. MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
  317. MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
  318. MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
  319. MX31_PIN_NFRB = IOMUX_PIN(16, 197),
  320. MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
  321. MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
  322. MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
  323. MX31_PIN_NFALE = IOMUX_PIN(12, 201),
  324. MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
  325. MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
  326. MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
  327. MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
  328. MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
  329. MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
  330. MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
  331. MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
  332. MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
  333. MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
  334. MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
  335. MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
  336. MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
  337. MX31_PIN_RW = IOMUX_PIN(0xff, 215),
  338. MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
  339. MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
  340. MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
  341. MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
  342. MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
  343. MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
  344. MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
  345. MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
  346. MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
  347. MX31_PIN_OE = IOMUX_PIN(0xff, 225),
  348. MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
  349. MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
  350. MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
  351. MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
  352. MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
  353. MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
  354. MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
  355. MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
  356. MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
  357. MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
  358. MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
  359. MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
  360. MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
  361. MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
  362. MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
  363. MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
  364. MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
  365. MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
  366. MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
  367. MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
  368. MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
  369. MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
  370. MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
  371. MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
  372. MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
  373. MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
  374. MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
  375. MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
  376. MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
  377. MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
  378. MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
  379. MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
  380. MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
  381. MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
  382. MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
  383. MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
  384. MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
  385. MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
  386. MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
  387. MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
  388. MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
  389. MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
  390. MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
  391. MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
  392. MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
  393. MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
  394. MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
  395. MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
  396. MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
  397. MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
  398. MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
  399. MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
  400. MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
  401. MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
  402. MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
  403. MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
  404. MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
  405. MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
  406. MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
  407. MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
  408. MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
  409. MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
  410. MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
  411. MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
  412. MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
  413. MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
  414. MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
  415. MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
  416. MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
  417. MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
  418. MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
  419. MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
  420. MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
  421. MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
  422. MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
  423. MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
  424. MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
  425. MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
  426. MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
  427. MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
  428. MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
  429. MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
  430. MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
  431. MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
  432. MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
  433. MX31_PIN_STX0 = IOMUX_PIN(33, 311),
  434. MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
  435. MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
  436. MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
  437. MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
  438. MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
  439. MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
  440. MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
  441. MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
  442. MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
  443. MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
  444. MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
  445. MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
  446. MX31_PIN_PWMO = IOMUX_PIN(9, 324),
  447. MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
  448. MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
  449. MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
  450. };
  451. /*
  452. * various IOMUX general purpose functions
  453. */
  454. enum iomux_gp_func {
  455. MUX_PGP_FIRI = 1 << 0,
  456. MUX_DDR_MODE = 1 << 1,
  457. MUX_PGP_CSPI_BB = 1 << 2,
  458. MUX_PGP_ATA_1 = 1 << 3,
  459. MUX_PGP_ATA_2 = 1 << 4,
  460. MUX_PGP_ATA_3 = 1 << 5,
  461. MUX_PGP_ATA_4 = 1 << 6,
  462. MUX_PGP_ATA_5 = 1 << 7,
  463. MUX_PGP_ATA_6 = 1 << 8,
  464. MUX_PGP_ATA_7 = 1 << 9,
  465. MUX_PGP_ATA_8 = 1 << 10,
  466. MUX_PGP_UH2 = 1 << 11,
  467. MUX_SDCTL_CSD0_SEL = 1 << 12,
  468. MUX_SDCTL_CSD1_SEL = 1 << 13,
  469. MUX_CSPI1_UART3 = 1 << 14,
  470. MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
  471. MUX_TAMPER_DETECT_EN = 1 << 16,
  472. MUX_PGP_USB_4WIRE = 1 << 17,
  473. MUX_PGP_USB_COMMON = 1 << 18,
  474. MUX_SDHC_MEMSTICK1 = 1 << 19,
  475. MUX_SDHC_MEMSTICK2 = 1 << 20,
  476. MUX_PGP_SPLL_BYP = 1 << 21,
  477. MUX_PGP_UPLL_BYP = 1 << 22,
  478. MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
  479. MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
  480. MUX_CSPI3_UART5_SEL = 1 << 25,
  481. MUX_PGP_ATA_9 = 1 << 26,
  482. MUX_PGP_USB_SUSPEND = 1 << 27,
  483. MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
  484. MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
  485. MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
  486. MUX_CLKO_DDR_MODE = 1 << 31,
  487. };
  488. /* Bit definitions for RCSR register in CCM */
  489. #define CCM_RCSR_NF16B (1 << 31)
  490. #define CCM_RCSR_NFMS (1 << 30)
  491. /* WEIM CS control registers */
  492. struct mx31_weim_cscr {
  493. u32 upper;
  494. u32 lower;
  495. u32 additional;
  496. u32 reserved;
  497. };
  498. struct mx31_weim {
  499. struct mx31_weim_cscr cscr[6];
  500. };
  501. /* ESD control registers */
  502. struct esdc_regs {
  503. u32 ctl0;
  504. u32 cfg0;
  505. u32 ctl1;
  506. u32 cfg1;
  507. u32 misc;
  508. u32 dly[5];
  509. u32 dlyl;
  510. };
  511. #endif
  512. #define ARCH_MXC
  513. #define __REG(x) (*((volatile u32 *)(x)))
  514. #define __REG16(x) (*((volatile u16 *)(x)))
  515. #define __REG8(x) (*((volatile u8 *)(x)))
  516. #define CCM_BASE 0x53f80000
  517. #define CCM_CCMR (CCM_BASE + 0x00)
  518. #define CCM_PDR0 (CCM_BASE + 0x04)
  519. #define CCM_PDR1 (CCM_BASE + 0x08)
  520. #define CCM_RCSR (CCM_BASE + 0x0c)
  521. #define CCM_MPCTL (CCM_BASE + 0x10)
  522. #define CCM_UPCTL (CCM_BASE + 0x14)
  523. #define CCM_SPCTL (CCM_BASE + 0x18)
  524. #define CCM_COSR (CCM_BASE + 0x1C)
  525. #define CCM_CGR0 (CCM_BASE + 0x20)
  526. #define CCM_CGR1 (CCM_BASE + 0x24)
  527. #define CCM_CGR2 (CCM_BASE + 0x28)
  528. #define CCMR_MDS (1 << 7)
  529. #define CCMR_SBYCS (1 << 4)
  530. #define CCMR_MPE (1 << 3)
  531. #define CCMR_PRCS_MASK (3 << 1)
  532. #define CCMR_FPM (1 << 1)
  533. #define CCMR_CKIH (2 << 1)
  534. #define MX31_IIM_BASE_ADDR 0x5001C000
  535. #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
  536. #define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
  537. #define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
  538. #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
  539. #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
  540. #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
  541. #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
  542. #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
  543. #define PDR0_MCU_PODF(x) ((x) & 0x7)
  544. #define PDR1_USB_PRDF(x) (((x) & 0x3) << 30)
  545. #define PDR1_USB_PODF(x) (((x) & 0x7) << 27)
  546. #define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24)
  547. #define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18)
  548. #define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15)
  549. #define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9)
  550. #define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6)
  551. #define PDR1_SSI1_PODF(x) ((x) & 0x3f)
  552. #define PLL_BRMO(x) (((x) & 0x1) << 31)
  553. #define PLL_PD(x) (((x) & 0xf) << 26)
  554. #define PLL_MFD(x) (((x) & 0x3ff) << 16)
  555. #define PLL_MFI(x) (((x) & 0xf) << 10)
  556. #define PLL_MFN(x) (((x) & 0x3ff) << 0)
  557. #define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f)
  558. #define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7)
  559. #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
  560. #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
  561. #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
  562. #define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3)
  563. #define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7)
  564. #define GET_PDR0_MCU_PODF(x) ((x) & 0x7)
  565. #define GET_PLL_PD(x) (((x) >> 26) & 0xf)
  566. #define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff)
  567. #define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
  568. #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
  569. #define WEIM_ESDCTL0 0xB8001000
  570. #define WEIM_ESDCFG0 0xB8001004
  571. #define WEIM_ESDCTL1 0xB8001008
  572. #define WEIM_ESDCFG1 0xB800100C
  573. #define WEIM_ESDMISC 0xB8001010
  574. #define UART1_BASE 0x43F90000
  575. #define UART2_BASE 0x43F94000
  576. #define UART3_BASE 0x5000C000
  577. #define UART4_BASE 0x43FB0000
  578. #define UART5_BASE 0x43FB4000
  579. #define I2C1_BASE_ADDR 0x43f80000
  580. #define I2C1_CLK_OFFSET 26
  581. #define I2C2_BASE_ADDR 0x43F98000
  582. #define I2C2_CLK_OFFSET 28
  583. #define I2C3_BASE_ADDR 0x43f84000
  584. #define I2C3_CLK_OFFSET 30
  585. #define ESDCTL_SDE (1 << 31)
  586. #define ESDCTL_CMD_RW (0 << 28)
  587. #define ESDCTL_CMD_PRECHARGE (1 << 28)
  588. #define ESDCTL_CMD_AUTOREFRESH (2 << 28)
  589. #define ESDCTL_CMD_LOADMODEREG (3 << 28)
  590. #define ESDCTL_CMD_MANUALREFRESH (4 << 28)
  591. #define ESDCTL_ROW_13 (2 << 24)
  592. #define ESDCTL_ROW(x) ((x) << 24)
  593. #define ESDCTL_COL_9 (1 << 20)
  594. #define ESDCTL_COL(x) ((x) << 20)
  595. #define ESDCTL_DSIZ(x) ((x) << 16)
  596. #define ESDCTL_SREFR(x) ((x) << 13)
  597. #define ESDCTL_PWDT(x) ((x) << 10)
  598. #define ESDCTL_FP(x) ((x) << 8)
  599. #define ESDCTL_BL(x) ((x) << 7)
  600. #define ESDCTL_PRCT(x) ((x) << 0)
  601. #define ESDCTL_BASE_ADDR 0xB8001000
  602. /* 13 fields of the upper CS control register */
  603. #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
  604. cnc, wsc, ew, wws, edc) \
  605. ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
  606. (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
  607. (wws) << 4 | (edc) << 0)
  608. /* 12 fields of the lower CS control register */
  609. #define CSCR_L(oea, oen, ebwa, ebwn, \
  610. csa, ebc, dsz, csn, psr, cre, wrap, csen) \
  611. ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
  612. (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
  613. (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
  614. /* 14 fields of the additional CS control register */
  615. #define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
  616. wwu, age, cnc2, fce) \
  617. ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
  618. (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
  619. (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
  620. (age) << 2 | (cnc2) << 1 | (fce) << 0)
  621. #define WEIM_BASE 0xb8002000
  622. #define IOMUXC_BASE 0x43FAC000
  623. #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
  624. #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
  625. #define IPU_BASE 0x53fc0000
  626. #define IPU_CONF IPU_BASE
  627. #define IPU_CONF_PXL_ENDIAN (1<<8)
  628. #define IPU_CONF_DU_EN (1<<7)
  629. #define IPU_CONF_DI_EN (1<<6)
  630. #define IPU_CONF_ADC_EN (1<<5)
  631. #define IPU_CONF_SDC_EN (1<<4)
  632. #define IPU_CONF_PF_EN (1<<3)
  633. #define IPU_CONF_ROT_EN (1<<2)
  634. #define IPU_CONF_IC_EN (1<<1)
  635. #define IPU_CONF_CSI_EN (1<<0)
  636. #define ARM_PPMRR 0x40000015
  637. #define WDOG1_BASE_ADDR 0x53FDC000
  638. /*
  639. * GPIO
  640. */
  641. #define GPIO1_BASE_ADDR 0x53FCC000
  642. #define GPIO2_BASE_ADDR 0x53FD0000
  643. #define GPIO3_BASE_ADDR 0x53FA4000
  644. #define GPIO_DR 0x00000000 /* data register */
  645. #define GPIO_GDIR 0x00000004 /* direction register */
  646. #define GPIO_PSR 0x00000008 /* pad status register */
  647. /*
  648. * Signal Multiplexing (IOMUX)
  649. */
  650. /* bits in the SW_MUX_CTL registers */
  651. #define MUX_CTL_OUT_GPIO_DR (0 << 4)
  652. #define MUX_CTL_OUT_FUNC (1 << 4)
  653. #define MUX_CTL_OUT_ALT1 (2 << 4)
  654. #define MUX_CTL_OUT_ALT2 (3 << 4)
  655. #define MUX_CTL_OUT_ALT3 (4 << 4)
  656. #define MUX_CTL_OUT_ALT4 (5 << 4)
  657. #define MUX_CTL_OUT_ALT5 (6 << 4)
  658. #define MUX_CTL_OUT_ALT6 (7 << 4)
  659. #define MUX_CTL_IN_NONE (0 << 0)
  660. #define MUX_CTL_IN_GPIO (1 << 0)
  661. #define MUX_CTL_IN_FUNC (2 << 0)
  662. #define MUX_CTL_IN_ALT1 (4 << 0)
  663. #define MUX_CTL_IN_ALT2 (8 << 0)
  664. #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
  665. #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
  666. #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
  667. #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
  668. /* Register offsets based on IOMUXC_BASE */
  669. /* 0x00 .. 0x7b */
  670. #define MUX_CTL_CSPI3_MISO 0x0c
  671. #define MUX_CTL_CSPI3_SCLK 0x0d
  672. #define MUX_CTL_CSPI3_SPI_RDY 0x0e
  673. #define MUX_CTL_CSPI3_MOSI 0x13
  674. #define MUX_CTL_SD1_DATA1 0x18
  675. #define MUX_CTL_SD1_DATA2 0x19
  676. #define MUX_CTL_SD1_DATA3 0x1a
  677. #define MUX_CTL_SD1_CMD 0x1d
  678. #define MUX_CTL_SD1_CLK 0x1e
  679. #define MUX_CTL_SD1_DATA0 0x1f
  680. #define MUX_CTL_USBH2_DATA1 0x40
  681. #define MUX_CTL_USBH2_DIR 0x44
  682. #define MUX_CTL_USBH2_STP 0x45
  683. #define MUX_CTL_USBH2_NXT 0x46
  684. #define MUX_CTL_USBH2_DATA0 0x47
  685. #define MUX_CTL_USBH2_CLK 0x4B
  686. #define MUX_CTL_TXD2 0x70
  687. #define MUX_CTL_RTS2 0x71
  688. #define MUX_CTL_CTS2 0x72
  689. #define MUX_CTL_RXD2 0x77
  690. #define MUX_CTL_RTS1 0x7c
  691. #define MUX_CTL_CTS1 0x7d
  692. #define MUX_CTL_DTR_DCE1 0x7e
  693. #define MUX_CTL_DSR_DCE1 0x7f
  694. #define MUX_CTL_CSPI2_SCLK 0x80
  695. #define MUX_CTL_CSPI2_SPI_RDY 0x81
  696. #define MUX_CTL_RXD1 0x82
  697. #define MUX_CTL_TXD1 0x83
  698. #define MUX_CTL_CSPI2_MISO 0x84
  699. #define MUX_CTL_CSPI2_SS0 0x85
  700. #define MUX_CTL_CSPI2_SS1 0x86
  701. #define MUX_CTL_CSPI2_SS2 0x87
  702. #define MUX_CTL_CSPI1_SS2 0x88
  703. #define MUX_CTL_CSPI1_SCLK 0x89
  704. #define MUX_CTL_CSPI1_SPI_RDY 0x8a
  705. #define MUX_CTL_CSPI2_MOSI 0x8b
  706. #define MUX_CTL_CSPI1_MOSI 0x8c
  707. #define MUX_CTL_CSPI1_MISO 0x8d
  708. #define MUX_CTL_CSPI1_SS0 0x8e
  709. #define MUX_CTL_CSPI1_SS1 0x8f
  710. #define MUX_CTL_STXD6 0x90
  711. #define MUX_CTL_SRXD6 0x91
  712. #define MUX_CTL_SCK6 0x92
  713. #define MUX_CTL_SFS6 0x93
  714. #define MUX_CTL_STXD3 0x9C
  715. #define MUX_CTL_SRXD3 0x9D
  716. #define MUX_CTL_SCK3 0x9E
  717. #define MUX_CTL_SFS3 0x9F
  718. #define MUX_CTL_NFC_WP 0xD0
  719. #define MUX_CTL_NFC_CE 0xD1
  720. #define MUX_CTL_NFC_RB 0xD2
  721. #define MUX_CTL_NFC_WE 0xD4
  722. #define MUX_CTL_NFC_RE 0xD5
  723. #define MUX_CTL_NFC_ALE 0xD6
  724. #define MUX_CTL_NFC_CLE 0xD7
  725. #define MUX_CTL_CAPTURE 0x150
  726. #define MUX_CTL_COMPARE 0x151
  727. /*
  728. * Helper macros for the MUX_[contact name]__[pin function] macros
  729. */
  730. #define IOMUX_MODE_POS 9
  731. #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
  732. /*
  733. * These macros can be used in mx31_gpio_mux() and have the form
  734. * MUX_[contact name]__[pin function]
  735. */
  736. #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
  737. #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
  738. #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
  739. #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
  740. #define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
  741. #define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
  742. #define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
  743. #define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
  744. #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
  745. #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
  746. #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
  747. #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
  748. #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
  749. #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
  750. IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
  751. #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
  752. #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
  753. #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
  754. #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
  755. #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
  756. #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
  757. #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
  758. IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
  759. #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
  760. #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
  761. #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
  762. /* PAD control registers for SDR/DDR */
  763. #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
  764. #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
  765. #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
  766. #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
  767. #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
  768. #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
  769. #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
  770. #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
  771. #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
  772. #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
  773. #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
  774. #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
  775. #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
  776. #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
  777. #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
  778. #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
  779. #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
  780. #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
  781. #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
  782. #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
  783. #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
  784. #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
  785. #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
  786. #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
  787. #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
  788. #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
  789. #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
  790. #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
  791. #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
  792. /*
  793. * Memory regions and CS
  794. */
  795. #define IPU_MEM_BASE 0x70000000
  796. #define CSD0_BASE 0x80000000
  797. #define CSD1_BASE 0x90000000
  798. #define CS0_BASE 0xA0000000
  799. #define CS1_BASE 0xA8000000
  800. #define CS2_BASE 0xB0000000
  801. #define CS3_BASE 0xB2000000
  802. #define CS4_BASE 0xB4000000
  803. #define CS4_PSRAM_BASE 0xB5000000
  804. #define CS5_BASE 0xB6000000
  805. #define PCMCIA_MEM_BASE 0xC0000000
  806. /*
  807. * NAND controller
  808. */
  809. #define NFC_BASE_ADDR 0xB8000000
  810. /* SD card controller */
  811. #define SDHC1_BASE_ADDR 0x50004000
  812. #define SDHC2_BASE_ADDR 0x50008000
  813. /*
  814. * Internal RAM (16KB)
  815. */
  816. #define IRAM_BASE_ADDR 0x1FFFC000
  817. #define IRAM_SIZE (16 * 1024)
  818. #define MX31_AIPS1_BASE_ADDR 0x43f00000
  819. #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
  820. #define IMX_USB_PORT_OFFSET 0x200
  821. /*
  822. * CSPI register definitions
  823. */
  824. #define MXC_CSPI
  825. #define MXC_CSPICTRL_EN (1 << 0)
  826. #define MXC_CSPICTRL_MODE (1 << 1)
  827. #define MXC_CSPICTRL_XCH (1 << 2)
  828. #define MXC_CSPICTRL_SMC (1 << 3)
  829. #define MXC_CSPICTRL_POL (1 << 4)
  830. #define MXC_CSPICTRL_PHA (1 << 5)
  831. #define MXC_CSPICTRL_SSCTL (1 << 6)
  832. #define MXC_CSPICTRL_SSPOL (1 << 7)
  833. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
  834. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
  835. #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
  836. #define MXC_CSPICTRL_TC (1 << 8)
  837. #define MXC_CSPICTRL_RXOVF (1 << 6)
  838. #define MXC_CSPICTRL_MAXBITS 0x1f
  839. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  840. #define MAX_SPI_BYTES 4
  841. #define MXC_SPI_BASE_ADDRESSES \
  842. 0x43fa4000, \
  843. 0x50010000, \
  844. 0x53f84000,
  845. /*
  846. * Generic timer support
  847. */
  848. #ifdef CONFIG_MX31_CLK32
  849. #define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32
  850. #else
  851. #define CONFIG_SYS_TIMER_RATE 32768
  852. #endif
  853. #endif /* __ASM_ARCH_MX31_IMX_REGS_H */