imx-regs.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  4. * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
  5. */
  6. #ifndef _IMX_REGS_H
  7. #define _IMX_REGS_H
  8. #include <asm/arch/regs-rtc.h>
  9. #ifndef __ASSEMBLY__
  10. extern void imx_gpio_mode (int gpio_mode);
  11. #ifdef CONFIG_MXC_UART
  12. extern void mx27_uart1_init_pins(void);
  13. #endif /* CONFIG_MXC_UART */
  14. #ifdef CONFIG_FEC_MXC
  15. extern void mx27_fec_init_pins(void);
  16. #endif /* CONFIG_FEC_MXC */
  17. #ifdef CONFIG_MMC_MXC
  18. extern void mx27_sd1_init_pins(void);
  19. extern void mx27_sd2_init_pins(void);
  20. #endif /* CONFIG_MMC_MXC */
  21. /* AIPI */
  22. struct aipi_regs {
  23. u32 psr0;
  24. u32 psr1;
  25. };
  26. /* System Control */
  27. struct system_control_regs {
  28. u32 res[5];
  29. u32 fmcr;
  30. u32 gpcr;
  31. u32 wbcr;
  32. u32 dscr1;
  33. u32 dscr2;
  34. u32 dscr3;
  35. u32 dscr4;
  36. u32 dscr5;
  37. u32 dscr6;
  38. u32 dscr7;
  39. u32 dscr8;
  40. u32 dscr9;
  41. u32 dscr10;
  42. u32 dscr11;
  43. u32 dscr12;
  44. u32 dscr13;
  45. u32 pscr;
  46. u32 pmcr;
  47. u32 res1;
  48. u32 dcvr0;
  49. u32 dcvr1;
  50. u32 dcvr2;
  51. u32 dcvr3;
  52. };
  53. /* Chip Select Registers */
  54. struct weim_regs {
  55. u32 cs0u; /* Chip Select 0 Upper Register */
  56. u32 cs0l; /* Chip Select 0 Lower Register */
  57. u32 cs0a; /* Chip Select 0 Addition Register */
  58. u32 pad0;
  59. u32 cs1u; /* Chip Select 1 Upper Register */
  60. u32 cs1l; /* Chip Select 1 Lower Register */
  61. u32 cs1a; /* Chip Select 1 Addition Register */
  62. u32 pad1;
  63. u32 cs2u; /* Chip Select 2 Upper Register */
  64. u32 cs2l; /* Chip Select 2 Lower Register */
  65. u32 cs2a; /* Chip Select 2 Addition Register */
  66. u32 pad2;
  67. u32 cs3u; /* Chip Select 3 Upper Register */
  68. u32 cs3l; /* Chip Select 3 Lower Register */
  69. u32 cs3a; /* Chip Select 3 Addition Register */
  70. u32 pad3;
  71. u32 cs4u; /* Chip Select 4 Upper Register */
  72. u32 cs4l; /* Chip Select 4 Lower Register */
  73. u32 cs4a; /* Chip Select 4 Addition Register */
  74. u32 pad4;
  75. u32 cs5u; /* Chip Select 5 Upper Register */
  76. u32 cs5l; /* Chip Select 5 Lower Register */
  77. u32 cs5a; /* Chip Select 5 Addition Register */
  78. u32 pad5;
  79. u32 eim; /* WEIM Configuration Register */
  80. };
  81. /* SDRAM Controller registers */
  82. struct esdramc_regs {
  83. /* Enhanced SDRAM Control Register 0 */
  84. u32 esdctl0;
  85. /* Enhanced SDRAM Configuration Register 0 */
  86. u32 esdcfg0;
  87. /* Enhanced SDRAM Control Register 1 */
  88. u32 esdctl1;
  89. /* Enhanced SDRAM Configuration Register 1 */
  90. u32 esdcfg1;
  91. /* Enhanced SDRAM Miscellanious Register */
  92. u32 esdmisc;
  93. };
  94. /* Watchdog Registers*/
  95. struct wdog_regs {
  96. u16 wcr;
  97. u16 wsr;
  98. u16 wstr;
  99. };
  100. /* PLL registers */
  101. struct pll_regs {
  102. u32 cscr; /* Clock Source Control Register */
  103. u32 mpctl0; /* MCU PLL Control Register 0 */
  104. u32 mpctl1; /* MCU PLL Control Register 1 */
  105. u32 spctl0; /* System PLL Control Register 0 */
  106. u32 spctl1; /* System PLL Control Register 1 */
  107. u32 osc26mctl; /* Oscillator 26M Register */
  108. u32 pcdr0; /* Peripheral Clock Divider Register 0 */
  109. u32 pcdr1; /* Peripheral Clock Divider Register 1 */
  110. u32 pccr0; /* Peripheral Clock Control Register 0 */
  111. u32 pccr1; /* Peripheral Clock Control Register 1 */
  112. u32 ccsr; /* Clock Control Status Register */
  113. };
  114. /*
  115. * Definitions for the clocksource registers
  116. */
  117. struct gpt_regs {
  118. u32 gpt_tctl;
  119. u32 gpt_tprer;
  120. u32 gpt_tcmp;
  121. u32 gpt_tcr;
  122. u32 gpt_tcn;
  123. u32 gpt_tstat;
  124. };
  125. /* IIM Control Registers */
  126. struct iim_regs {
  127. u32 iim_stat;
  128. u32 iim_statm;
  129. u32 iim_err;
  130. u32 iim_emask;
  131. u32 iim_fctl;
  132. u32 iim_ua;
  133. u32 iim_la;
  134. u32 iim_sdat;
  135. u32 iim_prev;
  136. u32 iim_srev;
  137. u32 iim_prg_p;
  138. u32 iim_scs0;
  139. u32 iim_scs1;
  140. u32 iim_scs2;
  141. u32 iim_scs3;
  142. u32 res[0x1f1];
  143. struct fuse_bank {
  144. u32 fuse_regs[0x20];
  145. u32 fuse_rsvd[0xe0];
  146. } bank[2];
  147. };
  148. struct fuse_bank0_regs {
  149. u32 fuse0_3[5];
  150. u32 mac_addr[6];
  151. u32 fuse10_31[0x16];
  152. };
  153. #endif
  154. #define ARCH_MXC
  155. #define IMX_IO_BASE 0x10000000
  156. #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
  157. #define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
  158. #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
  159. #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
  160. #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
  161. #define IMX_RTC_BASE (0x07000 + IMX_IO_BASE)
  162. #define UART1_BASE (0x0a000 + IMX_IO_BASE)
  163. #define UART2_BASE (0x0b000 + IMX_IO_BASE)
  164. #define UART3_BASE (0x0c000 + IMX_IO_BASE)
  165. #define UART4_BASE (0x0d000 + IMX_IO_BASE)
  166. #define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE)
  167. #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
  168. #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
  169. #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
  170. #define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
  171. #define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
  172. #define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE)
  173. #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
  174. #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
  175. #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
  176. #define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
  177. #define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
  178. #define IIM_BASE_ADDR IMX_IIM_BASE
  179. #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
  180. #define IMX_NFC_BASE (0xD8000000)
  181. #define IMX_ESD_BASE (0xD8001000)
  182. #define IMX_WEIM_BASE (0xD8002000)
  183. #define NFC_BASE_ADDR IMX_NFC_BASE
  184. /* FMCR System Control bit definition*/
  185. #define UART4_RXD_CTL (1 << 25)
  186. #define UART4_RTS_CTL (1 << 24)
  187. #define KP_COL6_CTL (1 << 18)
  188. #define KP_ROW7_CTL (1 << 17)
  189. #define KP_ROW6_CTL (1 << 16)
  190. #define PC_WAIT_B_CTL (1 << 14)
  191. #define PC_READY_CTL (1 << 13)
  192. #define PC_VS1_CTL (1 << 12)
  193. #define PC_VS2_CTL (1 << 11)
  194. #define PC_BVD1_CTL (1 << 10)
  195. #define PC_BVD2_CTL (1 << 9)
  196. #define IOS16_CTL (1 << 8)
  197. #define NF_FMS (1 << 5)
  198. #define NF_16BIT_SEL (1 << 4)
  199. #define SLCDC_SEL (1 << 2)
  200. #define SDCS1_SEL (1 << 1)
  201. #define SDCS0_SEL (1 << 0)
  202. /* important definition of some bits of WCR */
  203. #define WCR_WDE 0x04
  204. #define CSCR_MPEN (1 << 0)
  205. #define CSCR_SPEN (1 << 1)
  206. #define CSCR_FPM_EN (1 << 2)
  207. #define CSCR_OSC26M_DIS (1 << 3)
  208. #define CSCR_OSC26M_DIV1P5 (1 << 4)
  209. #define CSCR_AHB_DIV
  210. #define CSCR_ARM_DIV
  211. #define CSCR_ARM_SRC_MPLL (1 << 15)
  212. #define CSCR_MCU_SEL (1 << 16)
  213. #define CSCR_SP_SEL (1 << 17)
  214. #define CSCR_MPLL_RESTART (1 << 18)
  215. #define CSCR_SPLL_RESTART (1 << 19)
  216. #define CSCR_MSHC_SEL (1 << 20)
  217. #define CSCR_H264_SEL (1 << 21)
  218. #define CSCR_SSI1_SEL (1 << 22)
  219. #define CSCR_SSI2_SEL (1 << 23)
  220. #define CSCR_SD_CNT
  221. #define CSCR_USB_DIV
  222. #define CSCR_UPDATE_DIS (1 << 31)
  223. #define MPCTL1_BRMO (1 << 6)
  224. #define MPCTL1_LF (1 << 15)
  225. #define PCCR0_SSI2_EN (1 << 0)
  226. #define PCCR0_SSI1_EN (1 << 1)
  227. #define PCCR0_SLCDC_EN (1 << 2)
  228. #define PCCR0_SDHC3_EN (1 << 3)
  229. #define PCCR0_SDHC2_EN (1 << 4)
  230. #define PCCR0_SDHC1_EN (1 << 5)
  231. #define PCCR0_SDC_EN (1 << 6)
  232. #define PCCR0_SAHARA_EN (1 << 7)
  233. #define PCCR0_RTIC_EN (1 << 8)
  234. #define PCCR0_RTC_EN (1 << 9)
  235. #define PCCR0_PWM_EN (1 << 11)
  236. #define PCCR0_OWIRE_EN (1 << 12)
  237. #define PCCR0_MSHC_EN (1 << 13)
  238. #define PCCR0_LCDC_EN (1 << 14)
  239. #define PCCR0_KPP_EN (1 << 15)
  240. #define PCCR0_IIM_EN (1 << 16)
  241. #define PCCR0_I2C2_EN (1 << 17)
  242. #define PCCR0_I2C1_EN (1 << 18)
  243. #define PCCR0_GPT6_EN (1 << 19)
  244. #define PCCR0_GPT5_EN (1 << 20)
  245. #define PCCR0_GPT4_EN (1 << 21)
  246. #define PCCR0_GPT3_EN (1 << 22)
  247. #define PCCR0_GPT2_EN (1 << 23)
  248. #define PCCR0_GPT1_EN (1 << 24)
  249. #define PCCR0_GPIO_EN (1 << 25)
  250. #define PCCR0_FEC_EN (1 << 26)
  251. #define PCCR0_EMMA_EN (1 << 27)
  252. #define PCCR0_DMA_EN (1 << 28)
  253. #define PCCR0_CSPI3_EN (1 << 29)
  254. #define PCCR0_CSPI2_EN (1 << 30)
  255. #define PCCR0_CSPI1_EN (1 << 31)
  256. #define PCCR1_MSHC_BAUDEN (1 << 2)
  257. #define PCCR1_NFC_BAUDEN (1 << 3)
  258. #define PCCR1_SSI2_BAUDEN (1 << 4)
  259. #define PCCR1_SSI1_BAUDEN (1 << 5)
  260. #define PCCR1_H264_BAUDEN (1 << 6)
  261. #define PCCR1_PERCLK4_EN (1 << 7)
  262. #define PCCR1_PERCLK3_EN (1 << 8)
  263. #define PCCR1_PERCLK2_EN (1 << 9)
  264. #define PCCR1_PERCLK1_EN (1 << 10)
  265. #define PCCR1_HCLK_USB (1 << 11)
  266. #define PCCR1_HCLK_SLCDC (1 << 12)
  267. #define PCCR1_HCLK_SAHARA (1 << 13)
  268. #define PCCR1_HCLK_RTIC (1 << 14)
  269. #define PCCR1_HCLK_LCDC (1 << 15)
  270. #define PCCR1_HCLK_H264 (1 << 16)
  271. #define PCCR1_HCLK_FEC (1 << 17)
  272. #define PCCR1_HCLK_EMMA (1 << 18)
  273. #define PCCR1_HCLK_EMI (1 << 19)
  274. #define PCCR1_HCLK_DMA (1 << 20)
  275. #define PCCR1_HCLK_CSI (1 << 21)
  276. #define PCCR1_HCLK_BROM (1 << 22)
  277. #define PCCR1_HCLK_ATA (1 << 23)
  278. #define PCCR1_WDT_EN (1 << 24)
  279. #define PCCR1_USB_EN (1 << 25)
  280. #define PCCR1_UART6_EN (1 << 26)
  281. #define PCCR1_UART5_EN (1 << 27)
  282. #define PCCR1_UART4_EN (1 << 28)
  283. #define PCCR1_UART3_EN (1 << 29)
  284. #define PCCR1_UART2_EN (1 << 30)
  285. #define PCCR1_UART1_EN (1 << 31)
  286. /* SDRAM Controller registers bitfields */
  287. #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
  288. #define ESDCTL_BL (1 << 7)
  289. #define ESDCTL_FP (1 << 8)
  290. #define ESDCTL_PWDT(x) (((x) & 3) << 10)
  291. #define ESDCTL_SREFR(x) (((x) & 7) << 13)
  292. #define ESDCTL_DSIZ_16_UPPER (0 << 16)
  293. #define ESDCTL_DSIZ_16_LOWER (1 << 16)
  294. #define ESDCTL_DSIZ_32 (2 << 16)
  295. #define ESDCTL_COL8 (0 << 20)
  296. #define ESDCTL_COL9 (1 << 20)
  297. #define ESDCTL_COL10 (2 << 20)
  298. #define ESDCTL_ROW11 (0 << 24)
  299. #define ESDCTL_ROW12 (1 << 24)
  300. #define ESDCTL_ROW13 (2 << 24)
  301. #define ESDCTL_ROW14 (3 << 24)
  302. #define ESDCTL_ROW15 (4 << 24)
  303. #define ESDCTL_SP (1 << 27)
  304. #define ESDCTL_SMODE_NORMAL (0 << 28)
  305. #define ESDCTL_SMODE_PRECHARGE (1 << 28)
  306. #define ESDCTL_SMODE_AUTO_REF (2 << 28)
  307. #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
  308. #define ESDCTL_SMODE_MAN_REF (4 << 28)
  309. #define ESDCTL_SDE (1 << 31)
  310. #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
  311. #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
  312. #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
  313. #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
  314. #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
  315. #define ESDCFG_TWR (1 << 15)
  316. #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
  317. #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
  318. #define ESDCFG_TWTR (1 << 20)
  319. #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
  320. #define ESDMISC_RST (1 << 1)
  321. #define ESDMISC_MDDREN (1 << 2)
  322. #define ESDMISC_MDDR_DL_RST (1 << 3)
  323. #define ESDMISC_MDDR_MDIS (1 << 4)
  324. #define ESDMISC_LHD (1 << 5)
  325. #define ESDMISC_MA10_SHARE (1 << 6)
  326. #define ESDMISC_SDRAM_RDY (1 << 31)
  327. #define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
  328. #define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
  329. #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
  330. #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
  331. #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
  332. #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
  333. #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
  334. #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
  335. #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
  336. #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
  337. #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
  338. #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
  339. #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
  340. #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
  341. #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
  342. #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
  343. #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
  344. #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
  345. #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
  346. #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
  347. #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
  348. #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
  349. #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
  350. #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
  351. #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
  352. #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
  353. #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
  354. #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
  355. #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
  356. #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
  357. #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
  358. #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
  359. #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
  360. #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
  361. #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
  362. #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
  363. #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
  364. #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
  365. #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
  366. #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
  367. #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
  368. #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
  369. #define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
  370. #define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
  371. #define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
  372. #define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
  373. #define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
  374. #define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
  375. #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
  376. #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
  377. #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
  378. #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
  379. #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
  380. #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
  381. #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
  382. #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
  383. #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
  384. #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
  385. /* Clocksource Bitfields */
  386. #define TCTL_SWR (1 << 15) /* Software reset */
  387. #define TCTL_FRR (1 << 8) /* Freerun / restart */
  388. #define TCTL_CAP (3 << 6) /* Capture Edge */
  389. #define TCTL_OM (1 << 5) /* output mode */
  390. #define TCTL_IRQEN (1 << 4) /* interrupt enable */
  391. #define TCTL_CLKSOURCE 1 /* Clock source bit position */
  392. #define TCTL_TEN 1 /* Timer enable */
  393. #define TPRER_PRES 0xff /* Prescale */
  394. #define TSTAT_CAPT (1 << 1) /* Capture event */
  395. #define TSTAT_COMP 1 /* Compare event */
  396. #define GPIO1_BASE_ADDR 0x10015000
  397. #define GPIO2_BASE_ADDR 0x10015100
  398. #define GPIO3_BASE_ADDR 0x10015200
  399. #define GPIO4_BASE_ADDR 0x10015300
  400. #define GPIO5_BASE_ADDR 0x10015400
  401. #define GPIO6_BASE_ADDR 0x10015500
  402. #define GPIO_OUT (1 << 8)
  403. #define GPIO_IN (0 << 8)
  404. #define GPIO_PUEN (1 << 9)
  405. #define GPIO_PF (1 << 10)
  406. #define GPIO_AF (1 << 11)
  407. #define GPIO_OCR_SHIFT 12
  408. #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
  409. #define GPIO_AIN (0 << GPIO_OCR_SHIFT)
  410. #define GPIO_BIN (1 << GPIO_OCR_SHIFT)
  411. #define GPIO_CIN (2 << GPIO_OCR_SHIFT)
  412. #define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
  413. #define GPIO_AOUT_SHIFT 14
  414. #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
  415. #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
  416. #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
  417. #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
  418. #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
  419. #define GPIO_BOUT_SHIFT 16
  420. #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
  421. #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
  422. #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
  423. #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
  424. #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
  425. #define IIM_STAT_BUSY (1 << 7)
  426. #define IIM_STAT_PRGD (1 << 1)
  427. #define IIM_STAT_SNSD (1 << 0)
  428. #define IIM_ERR_PRGE (1 << 7)
  429. #define IIM_ERR_WPE (1 << 6)
  430. #define IIM_ERR_OPE (1 << 5)
  431. #define IIM_ERR_RPE (1 << 4)
  432. #define IIM_ERR_WLRE (1 << 3)
  433. #define IIM_ERR_SNSE (1 << 2)
  434. #define IIM_ERR_PARITYE (1 << 1)
  435. #endif /* _IMX_REGS_H */