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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. */
  6. #include <asm-offsets.h>
  7. #include <config.h>
  8. #include <linux/linkage.h>
  9. #include <asm/macro.h>
  10. #include <asm/armv8/mmu.h>
  11. /*************************************************************************
  12. *
  13. * Startup Code (reset vector)
  14. *
  15. *************************************************************************/
  16. .globl _start
  17. _start:
  18. #if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
  19. #include <asm/boot0-linux-kernel-header.h>
  20. #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
  21. /*
  22. * Various SoCs need something special and SoC-specific up front in
  23. * order to boot, allow them to set that in their boot0.h file and then
  24. * use it here.
  25. */
  26. #include <asm/arch/boot0.h>
  27. #else
  28. b reset
  29. #endif
  30. .align 3
  31. .globl _TEXT_BASE
  32. _TEXT_BASE:
  33. .quad CONFIG_SYS_TEXT_BASE
  34. /*
  35. * These are defined in the linker script.
  36. */
  37. .globl _end_ofs
  38. _end_ofs:
  39. .quad _end - _start
  40. .globl _bss_start_ofs
  41. _bss_start_ofs:
  42. .quad __bss_start - _start
  43. .globl _bss_end_ofs
  44. _bss_end_ofs:
  45. .quad __bss_end - _start
  46. reset:
  47. /* Allow the board to save important registers */
  48. b save_boot_params
  49. .globl save_boot_params_ret
  50. save_boot_params_ret:
  51. #if CONFIG_POSITION_INDEPENDENT
  52. /*
  53. * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
  54. * executed at a different address than it was linked at.
  55. */
  56. pie_fixup:
  57. adr x0, _start /* x0 <- Runtime value of _start */
  58. ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
  59. sub x9, x0, x1 /* x9 <- Run-vs-link offset */
  60. adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
  61. adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
  62. pie_fix_loop:
  63. ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
  64. ldr x4, [x2], #8 /* x4 <- addend */
  65. cmp w1, #1027 /* relative fixup? */
  66. bne pie_skip_reloc
  67. /* relative fix: store addend plus offset at dest location */
  68. add x0, x0, x9
  69. add x4, x4, x9
  70. str x4, [x0]
  71. pie_skip_reloc:
  72. cmp x2, x3
  73. b.lo pie_fix_loop
  74. pie_fixup_done:
  75. #endif
  76. #ifdef CONFIG_SYS_RESET_SCTRL
  77. bl reset_sctrl
  78. #endif
  79. #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
  80. .macro set_vbar, regname, reg
  81. msr \regname, \reg
  82. .endm
  83. adr x0, vectors
  84. #else
  85. .macro set_vbar, regname, reg
  86. .endm
  87. #endif
  88. /*
  89. * Could be EL3/EL2/EL1, Initial State:
  90. * Little Endian, MMU Disabled, i/dCache Disabled
  91. */
  92. switch_el x1, 3f, 2f, 1f
  93. 3: set_vbar vbar_el3, x0
  94. mrs x0, scr_el3
  95. orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
  96. msr scr_el3, x0
  97. msr cptr_el3, xzr /* Enable FP/SIMD */
  98. #ifdef COUNTER_FREQUENCY
  99. ldr x0, =COUNTER_FREQUENCY
  100. msr cntfrq_el0, x0 /* Initialize CNTFRQ */
  101. #endif
  102. b 0f
  103. 2: set_vbar vbar_el2, x0
  104. mov x0, #0x33ff
  105. msr cptr_el2, x0 /* Enable FP/SIMD */
  106. b 0f
  107. 1: set_vbar vbar_el1, x0
  108. mov x0, #3 << 20
  109. msr cpacr_el1, x0 /* Enable FP/SIMD */
  110. 0:
  111. isb
  112. /*
  113. * Enable SMPEN bit for coherency.
  114. * This register is not architectural but at the moment
  115. * this bit should be set for A53/A57/A72.
  116. */
  117. #ifdef CONFIG_ARMV8_SET_SMPEN
  118. switch_el x1, 3f, 1f, 1f
  119. 3:
  120. mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
  121. orr x0, x0, #0x40
  122. msr S3_1_c15_c2_1, x0
  123. isb
  124. 1:
  125. #endif
  126. /* Apply ARM core specific erratas */
  127. bl apply_core_errata
  128. /*
  129. * Cache/BPB/TLB Invalidate
  130. * i-cache is invalidated before enabled in icache_enable()
  131. * tlb is invalidated before mmu is enabled in dcache_enable()
  132. * d-cache is invalidated before enabled in dcache_enable()
  133. */
  134. /* Processor specific initialization */
  135. bl lowlevel_init
  136. #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
  137. branch_if_master x0, x1, master_cpu
  138. b spin_table_secondary_jump
  139. /* never return */
  140. #elif defined(CONFIG_ARMV8_MULTIENTRY)
  141. branch_if_master x0, x1, master_cpu
  142. /*
  143. * Slave CPUs
  144. */
  145. slave_cpu:
  146. wfe
  147. ldr x1, =CPU_RELEASE_ADDR
  148. ldr x0, [x1]
  149. cbz x0, slave_cpu
  150. br x0 /* branch to the given address */
  151. #endif /* CONFIG_ARMV8_MULTIENTRY */
  152. master_cpu:
  153. bl _main
  154. #ifdef CONFIG_SYS_RESET_SCTRL
  155. reset_sctrl:
  156. switch_el x1, 3f, 2f, 1f
  157. 3:
  158. mrs x0, sctlr_el3
  159. b 0f
  160. 2:
  161. mrs x0, sctlr_el2
  162. b 0f
  163. 1:
  164. mrs x0, sctlr_el1
  165. 0:
  166. ldr x1, =0xfdfffffa
  167. and x0, x0, x1
  168. switch_el x1, 6f, 5f, 4f
  169. 6:
  170. msr sctlr_el3, x0
  171. b 7f
  172. 5:
  173. msr sctlr_el2, x0
  174. b 7f
  175. 4:
  176. msr sctlr_el1, x0
  177. 7:
  178. dsb sy
  179. isb
  180. b __asm_invalidate_tlb_all
  181. ret
  182. #endif
  183. /*-----------------------------------------------------------------------*/
  184. WEAK(apply_core_errata)
  185. mov x29, lr /* Save LR */
  186. /* For now, we support Cortex-A53, Cortex-A57 specific errata */
  187. /* Check if we are running on a Cortex-A53 core */
  188. branch_if_a53_core x0, apply_a53_core_errata
  189. /* Check if we are running on a Cortex-A57 core */
  190. branch_if_a57_core x0, apply_a57_core_errata
  191. 0:
  192. mov lr, x29 /* Restore LR */
  193. ret
  194. apply_a53_core_errata:
  195. #ifdef CONFIG_ARM_ERRATA_855873
  196. mrs x0, midr_el1
  197. tst x0, #(0xf << 20)
  198. b.ne 0b
  199. mrs x0, midr_el1
  200. and x0, x0, #0xf
  201. cmp x0, #3
  202. b.lt 0b
  203. mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  204. /* Enable data cache clean as data cache clean/invalidate */
  205. orr x0, x0, #1 << 44
  206. msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  207. isb
  208. #endif
  209. b 0b
  210. apply_a57_core_errata:
  211. #ifdef CONFIG_ARM_ERRATA_828024
  212. mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  213. /* Disable non-allocate hint of w-b-n-a memory type */
  214. orr x0, x0, #1 << 49
  215. /* Disable write streaming no L1-allocate threshold */
  216. orr x0, x0, #3 << 25
  217. /* Disable write streaming no-allocate threshold */
  218. orr x0, x0, #3 << 27
  219. msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  220. isb
  221. #endif
  222. #ifdef CONFIG_ARM_ERRATA_826974
  223. mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  224. /* Disable speculative load execution ahead of a DMB */
  225. orr x0, x0, #1 << 59
  226. msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  227. isb
  228. #endif
  229. #ifdef CONFIG_ARM_ERRATA_833471
  230. mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  231. /* FPSCR write flush.
  232. * Note that in some cases where a flush is unnecessary this
  233. could impact performance. */
  234. orr x0, x0, #1 << 38
  235. msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  236. isb
  237. #endif
  238. #ifdef CONFIG_ARM_ERRATA_829520
  239. mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  240. /* Disable Indirect Predictor bit will prevent this erratum
  241. from occurring
  242. * Note that in some cases where a flush is unnecessary this
  243. could impact performance. */
  244. orr x0, x0, #1 << 4
  245. msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  246. isb
  247. #endif
  248. #ifdef CONFIG_ARM_ERRATA_833069
  249. mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  250. /* Disable Enable Invalidates of BTB bit */
  251. and x0, x0, #0xE
  252. msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  253. isb
  254. #endif
  255. b 0b
  256. ENDPROC(apply_core_errata)
  257. /*-----------------------------------------------------------------------*/
  258. WEAK(lowlevel_init)
  259. mov x29, lr /* Save LR */
  260. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  261. branch_if_slave x0, 1f
  262. ldr x0, =GICD_BASE
  263. bl gic_init_secure
  264. 1:
  265. #if defined(CONFIG_GICV3)
  266. ldr x0, =GICR_BASE
  267. bl gic_init_secure_percpu
  268. #elif defined(CONFIG_GICV2)
  269. ldr x0, =GICD_BASE
  270. ldr x1, =GICC_BASE
  271. bl gic_init_secure_percpu
  272. #endif
  273. #endif
  274. #ifdef CONFIG_ARMV8_MULTIENTRY
  275. branch_if_master x0, x1, 2f
  276. /*
  277. * Slave should wait for master clearing spin table.
  278. * This sync prevent salves observing incorrect
  279. * value of spin table and jumping to wrong place.
  280. */
  281. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  282. #ifdef CONFIG_GICV2
  283. ldr x0, =GICC_BASE
  284. #endif
  285. bl gic_wait_for_interrupt
  286. #endif
  287. /*
  288. * All slaves will enter EL2 and optionally EL1.
  289. */
  290. adr x4, lowlevel_in_el2
  291. ldr x5, =ES_TO_AARCH64
  292. bl armv8_switch_to_el2
  293. lowlevel_in_el2:
  294. #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
  295. adr x4, lowlevel_in_el1
  296. ldr x5, =ES_TO_AARCH64
  297. bl armv8_switch_to_el1
  298. lowlevel_in_el1:
  299. #endif
  300. #endif /* CONFIG_ARMV8_MULTIENTRY */
  301. 2:
  302. mov lr, x29 /* Restore LR */
  303. ret
  304. ENDPROC(lowlevel_init)
  305. WEAK(smp_kick_all_cpus)
  306. /* Kick secondary cpus up by SGI 0 interrupt */
  307. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  308. ldr x0, =GICD_BASE
  309. b gic_kick_secondary_cpus
  310. #endif
  311. ret
  312. ENDPROC(smp_kick_all_cpus)
  313. /*-----------------------------------------------------------------------*/
  314. ENTRY(c_runtime_cpu_setup)
  315. #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
  316. /* Relocate vBAR */
  317. adr x0, vectors
  318. switch_el x1, 3f, 2f, 1f
  319. 3: msr vbar_el3, x0
  320. b 0f
  321. 2: msr vbar_el2, x0
  322. b 0f
  323. 1: msr vbar_el1, x0
  324. 0:
  325. #endif
  326. ret
  327. ENDPROC(c_runtime_cpu_setup)
  328. WEAK(save_boot_params)
  329. b save_boot_params_ret /* back to my caller */
  330. ENDPROC(save_boot_params)