generic.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/mc_cgm_regs.h>
  14. #include <asm/arch/mc_me_regs.h>
  15. #include <asm/arch/mc_rgm_regs.h>
  16. #include <netdev.h>
  17. #include <div64.h>
  18. #include <errno.h>
  19. u32 get_cpu_rev(void)
  20. {
  21. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
  22. u32 cpu = readl(&mscmir->cpxtype);
  23. return cpu;
  24. }
  25. DECLARE_GLOBAL_DATA_PTR;
  26. static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
  27. u32 pllfd, u32 selected_output)
  28. {
  29. u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
  30. u32 plldv_rfdphi_div = 0, fout = 0;
  31. u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
  32. if (selected_output > DFS_MAXNUMBER) {
  33. return -1;
  34. }
  35. plldv_prediv =
  36. (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
  37. plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
  38. pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
  39. plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
  40. /* The formula for VCO is from TR manual, rev. D */
  41. vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
  42. if (selected_output != 0) {
  43. /* Determine the RFDPHI for PHI1 */
  44. plldv_rfdphi_div =
  45. (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
  46. PLLDIG_PLLDV_RFDPHI1_OFFSET;
  47. plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
  48. if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
  49. dfs_portn =
  50. readl(DFS_DVPORTn(pll, selected_output - 1));
  51. dfs_mfi =
  52. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  53. DFS_DVPORTn_MFI_OFFSET;
  54. dfs_mfn =
  55. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  56. DFS_DVPORTn_MFI_OFFSET;
  57. fout = vco / (dfs_mfi + (dfs_mfn / 256));
  58. } else {
  59. fout = vco / plldv_rfdphi_div;
  60. }
  61. } else {
  62. /* Determine the RFDPHI for PHI0 */
  63. plldv_rfdphi_div =
  64. (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
  65. PLLDIG_PLLDV_RFDPHI_OFFSET;
  66. fout = vco / plldv_rfdphi_div;
  67. }
  68. return fout;
  69. }
  70. /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
  71. static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
  72. u32 selected_output)
  73. {
  74. u32 plldv, pllfd;
  75. plldv = readl(PLLDIG_PLLDV(pll));
  76. pllfd = readl(PLLDIG_PLLFD(pll));
  77. return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
  78. }
  79. static u32 get_mcu_main_clk(void)
  80. {
  81. u32 coreclk_div;
  82. u32 sysclk_sel;
  83. u32 freq = 0;
  84. sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  85. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  86. coreclk_div =
  87. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
  88. coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  89. coreclk_div += 1;
  90. switch (sysclk_sel) {
  91. case MC_CGM_SC_SEL_FIRC:
  92. freq = FIRC_CLK_FREQ;
  93. break;
  94. case MC_CGM_SC_SEL_XOSC:
  95. freq = XOSC_CLK_FREQ;
  96. break;
  97. case MC_CGM_SC_SEL_ARMPLL:
  98. /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
  99. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
  100. break;
  101. case MC_CGM_SC_SEL_CLKDISABLE:
  102. printf("Sysclk is disabled\n");
  103. break;
  104. default:
  105. printf("unsupported system clock select\n");
  106. }
  107. return freq / coreclk_div;
  108. }
  109. static u32 get_sys_clk(u32 number)
  110. {
  111. u32 sysclk_div, sysclk_div_number;
  112. u32 sysclk_sel;
  113. u32 freq = 0;
  114. switch (number) {
  115. case 3:
  116. sysclk_div_number = 0;
  117. break;
  118. case 6:
  119. sysclk_div_number = 1;
  120. break;
  121. default:
  122. printf("unsupported system clock \n");
  123. return -1;
  124. }
  125. sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  126. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  127. sysclk_div =
  128. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
  129. MC_CGM_SC_DCn_PREDIV_MASK;
  130. sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  131. sysclk_div += 1;
  132. switch (sysclk_sel) {
  133. case MC_CGM_SC_SEL_FIRC:
  134. freq = FIRC_CLK_FREQ;
  135. break;
  136. case MC_CGM_SC_SEL_XOSC:
  137. freq = XOSC_CLK_FREQ;
  138. break;
  139. case MC_CGM_SC_SEL_ARMPLL:
  140. /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
  141. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
  142. break;
  143. case MC_CGM_SC_SEL_CLKDISABLE:
  144. printf("Sysclk is disabled\n");
  145. break;
  146. default:
  147. printf("unsupported system clock select\n");
  148. }
  149. return freq / sysclk_div;
  150. }
  151. static u32 get_peripherals_clk(void)
  152. {
  153. u32 aux5clk_div;
  154. u32 freq = 0;
  155. aux5clk_div =
  156. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
  157. MC_CGM_ACn_DCm_PREDIV_MASK;
  158. aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  159. aux5clk_div += 1;
  160. freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
  161. return freq / aux5clk_div;
  162. }
  163. static u32 get_uart_clk(void)
  164. {
  165. u32 auxclk3_div, auxclk3_sel, freq = 0;
  166. auxclk3_sel =
  167. readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
  168. auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
  169. auxclk3_div =
  170. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
  171. MC_CGM_ACn_DCm_PREDIV_MASK;
  172. auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  173. auxclk3_div += 1;
  174. switch (auxclk3_sel) {
  175. case MC_CGM_ACn_SEL_FIRC:
  176. freq = FIRC_CLK_FREQ;
  177. break;
  178. case MC_CGM_ACn_SEL_XOSC:
  179. freq = XOSC_CLK_FREQ;
  180. break;
  181. case MC_CGM_ACn_SEL_PERPLLDIVX:
  182. freq = get_peripherals_clk() / 3;
  183. break;
  184. case MC_CGM_ACn_SEL_SYSCLK:
  185. freq = get_sys_clk(6);
  186. break;
  187. default:
  188. printf("unsupported system clock select\n");
  189. }
  190. return freq / auxclk3_div;
  191. }
  192. static u32 get_fec_clk(void)
  193. {
  194. u32 aux2clk_div;
  195. u32 freq = 0;
  196. aux2clk_div =
  197. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
  198. MC_CGM_ACn_DCm_PREDIV_MASK;
  199. aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  200. aux2clk_div += 1;
  201. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
  202. return freq / aux2clk_div;
  203. }
  204. static u32 get_usdhc_clk(void)
  205. {
  206. u32 aux15clk_div;
  207. u32 freq = 0;
  208. aux15clk_div =
  209. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
  210. MC_CGM_ACn_DCm_PREDIV_MASK;
  211. aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  212. aux15clk_div += 1;
  213. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
  214. return freq / aux15clk_div;
  215. }
  216. static u32 get_i2c_clk(void)
  217. {
  218. return get_peripherals_clk();
  219. }
  220. /* return clocks in Hz */
  221. unsigned int mxc_get_clock(enum mxc_clock clk)
  222. {
  223. switch (clk) {
  224. case MXC_ARM_CLK:
  225. return get_mcu_main_clk();
  226. case MXC_PERIPHERALS_CLK:
  227. return get_peripherals_clk();
  228. case MXC_UART_CLK:
  229. return get_uart_clk();
  230. case MXC_FEC_CLK:
  231. return get_fec_clk();
  232. case MXC_I2C_CLK:
  233. return get_i2c_clk();
  234. case MXC_USDHC_CLK:
  235. return get_usdhc_clk();
  236. default:
  237. break;
  238. }
  239. printf("Error: Unsupported function to read the frequency! \
  240. Please define it correctly!");
  241. return -1;
  242. }
  243. /* Not yet implemented - int soc_clk_dump(); */
  244. #if defined(CONFIG_DISPLAY_CPUINFO)
  245. static char *get_reset_cause(void)
  246. {
  247. u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
  248. switch (cause) {
  249. case F_SWT4:
  250. return "WDOG";
  251. case F_JTAG:
  252. return "JTAG";
  253. case F_FCCU_SOFT:
  254. return "FCCU soft reaction";
  255. case F_FCCU_HARD:
  256. return "FCCU hard reaction";
  257. case F_SOFT_FUNC:
  258. return "Software Functional reset";
  259. case F_ST_DONE:
  260. return "Self Test done reset";
  261. case F_EXT_RST:
  262. return "External reset";
  263. default:
  264. return "unknown reset";
  265. }
  266. }
  267. #define SRC_SCR_SW_RST (1<<12)
  268. void reset_cpu(ulong addr)
  269. {
  270. printf("Feature not supported.\n");
  271. };
  272. int print_cpuinfo(void)
  273. {
  274. printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
  275. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  276. printf("Reset cause: %s\n", get_reset_cause());
  277. return 0;
  278. }
  279. #endif
  280. int cpu_eth_init(struct bd_info * bis)
  281. {
  282. int rc = -ENODEV;
  283. #if defined(CONFIG_FEC_MXC)
  284. rc = fecmxc_initialize(bis);
  285. #endif
  286. return rc;
  287. }
  288. int get_clocks(void)
  289. {
  290. #ifdef CONFIG_FSL_ESDHC_IMX
  291. gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
  292. #endif
  293. return 0;
  294. }