lx2160a_serdes.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <asm/arch/fsl_serdes.h>
  7. struct serdes_config {
  8. u8 protocol;
  9. u8 lanes[SRDS_MAX_LANES];
  10. };
  11. static struct serdes_config serdes1_cfg_tbl[] = {
  12. /* SerDes 1 */
  13. {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
  14. {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } },
  15. {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4,
  16. XFI3 } },
  17. {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4,
  18. SGMII3 } },
  19. {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1,
  20. PCIE1 } },
  21. {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4,
  22. XFI3 } },
  23. {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4,
  24. XFI3 } },
  25. {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } },
  26. {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4,
  27. PCIE1 } },
  28. {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } },
  29. {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } },
  30. {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
  31. {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1,
  32. _100GE1 } },
  33. {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1,
  34. _100GE1 } },
  35. {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } },
  36. {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } },
  37. {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } },
  38. {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4,
  39. XFI3 } },
  40. {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } },
  41. {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1,
  42. _40GE1 } },
  43. {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4,
  44. _25GE3 } },
  45. {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
  46. {}
  47. };
  48. static struct serdes_config serdes2_cfg_tbl[] = {
  49. /* SerDes 2 */
  50. {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } },
  51. {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
  52. {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  53. {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
  54. {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } },
  55. {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13,
  56. XFI14 } },
  57. {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13,
  58. XFI14 } },
  59. {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } },
  60. {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13,
  61. SGMII14} },
  62. {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4,
  63. PCIE4 } },
  64. {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13,
  65. SGMII14 } },
  66. {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1,
  67. SATA2 } },
  68. {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } },
  69. {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13,
  70. SGMII14 } },
  71. {}
  72. };
  73. static struct serdes_config serdes3_cfg_tbl[] = {
  74. /* SerDes 3 */
  75. {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } },
  76. {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } },
  77. {}
  78. };
  79. static struct serdes_config *serdes_cfg_tbl[] = {
  80. serdes1_cfg_tbl,
  81. serdes2_cfg_tbl,
  82. serdes3_cfg_tbl,
  83. };
  84. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  85. {
  86. struct serdes_config *ptr;
  87. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  88. return 0;
  89. ptr = serdes_cfg_tbl[serdes];
  90. while (ptr->protocol) {
  91. if (ptr->protocol == cfg)
  92. return ptr->lanes[lane];
  93. ptr++;
  94. }
  95. return 0;
  96. }
  97. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  98. {
  99. int i;
  100. struct serdes_config *ptr;
  101. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  102. return 0;
  103. ptr = serdes_cfg_tbl[serdes];
  104. while (ptr->protocol) {
  105. if (ptr->protocol == prtcl)
  106. break;
  107. ptr++;
  108. }
  109. if (!ptr->protocol)
  110. return 0;
  111. for (i = 0; i < SRDS_MAX_LANES; i++) {
  112. if (ptr->lanes[i] != NONE)
  113. return 1;
  114. }
  115. return 0;
  116. }