ls1046a_serdes.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <asm/arch/fsl_serdes.h>
  8. #include <asm/arch/immap_lsch2.h>
  9. struct serdes_config {
  10. u32 protocol;
  11. u8 lanes[SRDS_MAX_LANES];
  12. };
  13. static struct serdes_config serdes1_cfg_tbl[] = {
  14. /* SerDes 1 */
  15. {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
  16. SGMII_FM1_DTSEC6} },
  17. {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
  18. SGMII_FM1_DTSEC6} },
  19. {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
  20. SGMII_FM1_DTSEC6} },
  21. {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
  22. SGMII_FM1_DTSEC6} },
  23. {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
  24. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  25. {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
  26. {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
  27. {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
  28. {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
  29. SGMII_FM1_DTSEC6} },
  30. {0x3363, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, PCIE1,
  31. SGMII_FM1_DTSEC6} },
  32. {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
  33. SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  34. {0x3040, {SGMII_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
  35. {}
  36. };
  37. static struct serdes_config serdes2_cfg_tbl[] = {
  38. /* SerDes 2 */
  39. {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
  40. {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
  41. {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
  42. {0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
  43. {0x0506, {NONE, PCIE2, NONE, PCIE3} },
  44. {0x0559, {NONE, PCIE2, PCIE3, SATA1} },
  45. {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
  46. {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
  47. {}
  48. };
  49. static struct serdes_config *serdes_cfg_tbl[] = {
  50. serdes1_cfg_tbl,
  51. serdes2_cfg_tbl,
  52. };
  53. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  54. {
  55. struct serdes_config *ptr;
  56. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  57. return 0;
  58. ptr = serdes_cfg_tbl[serdes];
  59. while (ptr->protocol) {
  60. if (ptr->protocol == cfg)
  61. return ptr->lanes[lane];
  62. ptr++;
  63. }
  64. return 0;
  65. }
  66. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  67. {
  68. int i;
  69. struct serdes_config *ptr;
  70. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  71. return 0;
  72. ptr = serdes_cfg_tbl[serdes];
  73. while (ptr->protocol) {
  74. if (ptr->protocol == prtcl)
  75. break;
  76. ptr++;
  77. }
  78. if (!ptr->protocol)
  79. return 0;
  80. for (i = 0; i < SRDS_MAX_LANES; i++) {
  81. if (ptr->lanes[i] != NONE)
  82. return 1;
  83. }
  84. return 0;
  85. }