Kconfig 6.4 KB

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  1. if ARM64
  2. config ARMV8_SPL_EXCEPTION_VECTORS
  3. bool "Install crash dump exception vectors"
  4. depends on SPL
  5. default n
  6. help
  7. The default exception vector table is only used for the crash
  8. dump, but still takes quite a lot of space in the image size.
  9. Say N here if you are running out of code space in the image
  10. and want to save some space at the cost of less debugging info.
  11. config ARMV8_MULTIENTRY
  12. bool "Enable multiple CPUs to enter into U-Boot"
  13. config ARMV8_SET_SMPEN
  14. bool "Enable data coherency with other cores in cluster"
  15. help
  16. Say Y here if there is not any trust firmware to set
  17. CPUECTLR_EL1.SMPEN bit before U-Boot.
  18. For A53, it enables data coherency with other cores in the
  19. cluster, and for A57/A72, it enables receiving of instruction
  20. cache and TLB maintenance operations.
  21. Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
  22. for single core systems. Unfortunately write access to this
  23. register may be controlled by EL3/EL2 firmware. To be more
  24. precise, by default (if there is EL2/EL3 firmware running)
  25. this register is RO for NS EL1.
  26. This switch can be used to avoid writing to CPUECTLR_EL1,
  27. it can be safely enabled when EL2/EL3 initialized SMPEN bit
  28. or when CPU implementation doesn't include that register.
  29. config ARMV8_SPIN_TABLE
  30. bool "Support spin-table enable method"
  31. depends on ARMV8_MULTIENTRY && OF_LIBFDT
  32. help
  33. Say Y here to support "spin-table" enable method for booting Linux.
  34. To use this feature, you must do:
  35. - Specify enable-method = "spin-table" in each CPU node in the
  36. Device Tree you are using to boot the kernel
  37. - Bring secondary CPUs into U-Boot proper in a board specific
  38. manner. This must be done *after* relocation. Otherwise, the
  39. secondary CPUs will spin in unprotected memory area because the
  40. master CPU protects the relocated spin code.
  41. U-Boot automatically does:
  42. - Set "cpu-release-addr" property of each CPU node
  43. (overwrites it if already exists).
  44. - Reserve the code for the spin-table and the release address
  45. via a /memreserve/ region in the Device Tree.
  46. menu "ARMv8 secure monitor firmware"
  47. config ARMV8_SEC_FIRMWARE_SUPPORT
  48. bool "Enable ARMv8 secure monitor firmware framework support"
  49. select FIT
  50. select OF_LIBFDT
  51. help
  52. This framework is aimed at making secure monitor firmware load
  53. process brief.
  54. Note: Only FIT format image is supported.
  55. You should prepare and provide the below information:
  56. - Address of secure firmware.
  57. - Address to hold the return address from secure firmware.
  58. - Secure firmware FIT image related information.
  59. Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
  60. - The target exception level that secure monitor firmware will
  61. return to.
  62. config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  63. bool "Enable ARMv8 secure monitor firmware framework support for SPL"
  64. select SPL_FIT
  65. select SPL_OF_LIBFDT
  66. help
  67. Say Y here to support this framework in SPL phase.
  68. config SPL_RECOVER_DATA_SECTION
  69. bool "save/restore SPL data section"
  70. help
  71. Say Y here to save SPL data section for cold boot, and restore
  72. at warm boot in SPL phase.
  73. config SEC_FIRMWARE_ARMV8_PSCI
  74. bool "PSCI implementation in secure monitor firmware"
  75. depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  76. help
  77. This config enables the ARMv8 PSCI implementation in secure monitor
  78. firmware. This is a private PSCI implementation and different from
  79. those implemented under the common ARMv8 PSCI framework.
  80. config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
  81. bool "ARMv8 secure monitor firmware ERET address byteorder swap"
  82. depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  83. help
  84. Say Y here when the endianness of the register or memory holding the
  85. Secure firmware exception return address is different with core's.
  86. endmenu
  87. config PSCI_RESET
  88. bool "Use PSCI for reset and shutdown"
  89. default y
  90. select ARM_SMCCC if OF_CONTROL
  91. depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
  92. !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
  93. !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
  94. !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
  95. !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
  96. !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
  97. !TARGET_LS1012AFRWY && \
  98. !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
  99. !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
  100. !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
  101. !TARGET_LS1046AFRWY && \
  102. !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
  103. !TARGET_LX2160AQDS && \
  104. !ARCH_UNIPHIER && !TARGET_S32V234EVB
  105. help
  106. Most armv8 systems have PSCI support enabled in EL3, either through
  107. ARM Trusted Firmware or other firmware.
  108. On these systems, we do not need to implement system reset manually,
  109. but can instead rely on higher level firmware to deal with it.
  110. Select Y here to make use of PSCI calls for system reset
  111. config ARMV8_PSCI
  112. bool "Enable PSCI support" if EXPERT
  113. default n
  114. help
  115. PSCI is Power State Coordination Interface defined by ARM.
  116. The PSCI in U-boot provides a general framework and each platform
  117. can implement their own specific PSCI functions.
  118. Say Y here to enable PSCI support on ARMv8 platform.
  119. config ARMV8_PSCI_NR_CPUS
  120. int "Maximum supported CPUs for PSCI"
  121. depends on ARMV8_PSCI
  122. default 4
  123. help
  124. The maximum number of CPUs supported in the PSCI firmware.
  125. It is no problem to set a larger value than the number of CPUs in
  126. the actual hardware implementation.
  127. config ARMV8_PSCI_CPUS_PER_CLUSTER
  128. int "Number of CPUs per cluster"
  129. depends on ARMV8_PSCI
  130. default 0
  131. help
  132. The number of CPUs per cluster, suppose each cluster has same number
  133. of CPU cores, platforms with asymmetric clusters don't apply here.
  134. A value 0 or no definition of it works for single cluster system.
  135. System with multi-cluster should difine their own exact value.
  136. config ARMV8_EA_EL3_FIRST
  137. bool "External aborts and SError interrupt exception are taken in EL3"
  138. default n
  139. help
  140. Exception handling at all exception levels for External Abort and
  141. SError interrupt exception are taken in EL3.
  142. if SYS_HAS_ARMV8_SECURE_BASE
  143. config ARMV8_SECURE_BASE
  144. hex "Secure address for PSCI image"
  145. depends on ARMV8_PSCI
  146. help
  147. Address for placing the PSCI text, data and stack sections.
  148. If not defined, the PSCI sections are placed together with the u-boot
  149. but platform can choose to place PSCI code image separately in other
  150. places such as some secure RAM built-in SOC etc.
  151. endif
  152. endif