generic.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <command.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/cache.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <asm/mach-imx/sys_proto.h>
  17. #include <env.h>
  18. #include <netdev.h>
  19. #ifdef CONFIG_FSL_ESDHC_IMX
  20. #include <fsl_esdhc_imx.h>
  21. #endif
  22. #ifdef CONFIG_FSL_ESDHC_IMX
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #endif
  25. static char soc_type[] = "xx0";
  26. #ifdef CONFIG_MXC_OCOTP
  27. void enable_ocotp_clk(unsigned char enable)
  28. {
  29. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  30. u32 reg;
  31. reg = readl(&ccm->ccgr6);
  32. if (enable)
  33. reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
  34. else
  35. reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
  36. writel(reg, &ccm->ccgr6);
  37. }
  38. #endif
  39. static u32 get_mcu_main_clk(void)
  40. {
  41. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  42. u32 ccm_ccsr, ccm_cacrr, armclk_div;
  43. u32 sysclk_sel, pll_pfd_sel = 0;
  44. u32 freq = 0;
  45. ccm_ccsr = readl(&ccm->ccsr);
  46. sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
  47. sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
  48. ccm_cacrr = readl(&ccm->cacrr);
  49. armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
  50. armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
  51. armclk_div += 1;
  52. switch (sysclk_sel) {
  53. case 0:
  54. freq = FASE_CLK_FREQ;
  55. break;
  56. case 1:
  57. freq = SLOW_CLK_FREQ;
  58. break;
  59. case 2:
  60. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
  61. pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
  62. if (pll_pfd_sel == 0)
  63. freq = PLL2_MAIN_FREQ;
  64. else if (pll_pfd_sel == 1)
  65. freq = PLL2_PFD1_FREQ;
  66. else if (pll_pfd_sel == 2)
  67. freq = PLL2_PFD2_FREQ;
  68. else if (pll_pfd_sel == 3)
  69. freq = PLL2_PFD3_FREQ;
  70. else if (pll_pfd_sel == 4)
  71. freq = PLL2_PFD4_FREQ;
  72. break;
  73. case 3:
  74. freq = PLL2_MAIN_FREQ;
  75. break;
  76. case 4:
  77. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
  78. pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
  79. if (pll_pfd_sel == 0)
  80. freq = PLL1_MAIN_FREQ;
  81. else if (pll_pfd_sel == 1)
  82. freq = PLL1_PFD1_FREQ;
  83. else if (pll_pfd_sel == 2)
  84. freq = PLL1_PFD2_FREQ;
  85. else if (pll_pfd_sel == 3)
  86. freq = PLL1_PFD3_FREQ;
  87. else if (pll_pfd_sel == 4)
  88. freq = PLL1_PFD4_FREQ;
  89. break;
  90. case 5:
  91. freq = PLL3_MAIN_FREQ;
  92. break;
  93. default:
  94. printf("unsupported system clock select\n");
  95. }
  96. return freq / armclk_div;
  97. }
  98. static u32 get_bus_clk(void)
  99. {
  100. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  101. u32 ccm_cacrr, busclk_div;
  102. ccm_cacrr = readl(&ccm->cacrr);
  103. busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
  104. busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
  105. busclk_div += 1;
  106. return get_mcu_main_clk() / busclk_div;
  107. }
  108. static u32 get_ipg_clk(void)
  109. {
  110. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  111. u32 ccm_cacrr, ipgclk_div;
  112. ccm_cacrr = readl(&ccm->cacrr);
  113. ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
  114. ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
  115. ipgclk_div += 1;
  116. return get_bus_clk() / ipgclk_div;
  117. }
  118. static u32 get_uart_clk(void)
  119. {
  120. return get_ipg_clk();
  121. }
  122. static u32 get_sdhc_clk(void)
  123. {
  124. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  125. u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
  126. u32 freq = 0;
  127. ccm_cscmr1 = readl(&ccm->cscmr1);
  128. sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
  129. sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
  130. ccm_cscdr2 = readl(&ccm->cscdr2);
  131. sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
  132. sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
  133. sdhc_clk_div += 1;
  134. switch (sdhc_clk_sel) {
  135. case 0:
  136. freq = PLL3_MAIN_FREQ;
  137. break;
  138. case 1:
  139. freq = PLL3_PFD3_FREQ;
  140. break;
  141. case 2:
  142. freq = PLL1_PFD3_FREQ;
  143. break;
  144. case 3:
  145. freq = get_bus_clk();
  146. break;
  147. }
  148. return freq / sdhc_clk_div;
  149. }
  150. u32 get_fec_clk(void)
  151. {
  152. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  153. u32 ccm_cscmr2, rmii_clk_sel;
  154. u32 freq = 0;
  155. ccm_cscmr2 = readl(&ccm->cscmr2);
  156. rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
  157. rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
  158. switch (rmii_clk_sel) {
  159. case 0:
  160. freq = ENET_EXTERNAL_CLK;
  161. break;
  162. case 1:
  163. freq = AUDIO_EXTERNAL_CLK;
  164. break;
  165. case 2:
  166. freq = PLL5_MAIN_FREQ;
  167. break;
  168. case 3:
  169. freq = PLL5_MAIN_FREQ / 2;
  170. break;
  171. }
  172. return freq;
  173. }
  174. static u32 get_i2c_clk(void)
  175. {
  176. return get_ipg_clk();
  177. }
  178. static u32 get_dspi_clk(void)
  179. {
  180. return get_ipg_clk();
  181. }
  182. u32 get_lpuart_clk(void)
  183. {
  184. return get_uart_clk();
  185. }
  186. unsigned int mxc_get_clock(enum mxc_clock clk)
  187. {
  188. switch (clk) {
  189. case MXC_ARM_CLK:
  190. return get_mcu_main_clk();
  191. case MXC_BUS_CLK:
  192. return get_bus_clk();
  193. case MXC_IPG_CLK:
  194. return get_ipg_clk();
  195. case MXC_UART_CLK:
  196. return get_uart_clk();
  197. case MXC_ESDHC_CLK:
  198. return get_sdhc_clk();
  199. case MXC_FEC_CLK:
  200. return get_fec_clk();
  201. case MXC_I2C_CLK:
  202. return get_i2c_clk();
  203. case MXC_DSPI_CLK:
  204. return get_dspi_clk();
  205. default:
  206. break;
  207. }
  208. return -1;
  209. }
  210. /* Dump some core clocks */
  211. int do_vf610_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  212. char *const argv[])
  213. {
  214. printf("\n");
  215. printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  216. printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
  217. printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
  218. return 0;
  219. }
  220. U_BOOT_CMD(
  221. clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
  222. "display clocks",
  223. ""
  224. );
  225. #ifdef CONFIG_FEC_MXC
  226. __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  227. {
  228. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  229. struct fuse_bank *bank = &ocotp->bank[4];
  230. struct fuse_bank4_regs *fuse =
  231. (struct fuse_bank4_regs *)bank->fuse_regs;
  232. u32 value = readl(&fuse->mac_addr0);
  233. mac[0] = (value >> 8);
  234. mac[1] = value;
  235. value = readl(&fuse->mac_addr1);
  236. mac[2] = value >> 24;
  237. mac[3] = value >> 16;
  238. mac[4] = value >> 8;
  239. mac[5] = value;
  240. }
  241. #endif
  242. u32 get_cpu_rev(void)
  243. {
  244. return MXC_CPU_VF610 << 12;
  245. }
  246. #if defined(CONFIG_DISPLAY_CPUINFO)
  247. static char *get_reset_cause(void)
  248. {
  249. u32 cause;
  250. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  251. cause = readl(&src_regs->srsr);
  252. writel(cause, &src_regs->srsr);
  253. if (cause & SRC_SRSR_POR_RST)
  254. return "POWER ON RESET";
  255. else if (cause & SRC_SRSR_WDOG_A5)
  256. return "WDOG A5";
  257. else if (cause & SRC_SRSR_WDOG_M4)
  258. return "WDOG M4";
  259. else if (cause & SRC_SRSR_JTAG_RST)
  260. return "JTAG HIGH-Z";
  261. else if (cause & SRC_SRSR_SW_RST)
  262. return "SW RESET";
  263. else if (cause & SRC_SRSR_RESETB)
  264. return "EXTERNAL RESET";
  265. else
  266. return "unknown reset";
  267. }
  268. int print_cpuinfo(void)
  269. {
  270. printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
  271. soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
  272. printf("Reset cause: %s\n", get_reset_cause());
  273. return 0;
  274. }
  275. #endif
  276. int arch_cpu_init(void)
  277. {
  278. struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
  279. soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
  280. soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
  281. return 0;
  282. }
  283. #ifdef CONFIG_ARCH_MISC_INIT
  284. int arch_misc_init(void)
  285. {
  286. char soc[6];
  287. strcpy(soc, "vf");
  288. strcat(soc, soc_type);
  289. env_set("soc", soc);
  290. return 0;
  291. }
  292. #endif
  293. int cpu_eth_init(struct bd_info *bis)
  294. {
  295. int rc = -ENODEV;
  296. #if defined(CONFIG_FEC_MXC)
  297. rc = fecmxc_initialize(bis);
  298. #endif
  299. return rc;
  300. }
  301. #ifdef CONFIG_FSL_ESDHC_IMX
  302. int cpu_mmc_init(struct bd_info *bis)
  303. {
  304. return fsl_esdhc_mmc_init(bis);
  305. }
  306. #endif
  307. int get_clocks(void)
  308. {
  309. #ifdef CONFIG_FSL_ESDHC_IMX
  310. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  311. #endif
  312. return 0;
  313. }
  314. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  315. void enable_caches(void)
  316. {
  317. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  318. enum dcache_option option = DCACHE_WRITETHROUGH;
  319. #else
  320. enum dcache_option option = DCACHE_WRITEBACK;
  321. #endif
  322. dcache_enable();
  323. icache_enable();
  324. /* Enable caching on OCRAM */
  325. mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
  326. }
  327. #endif
  328. #ifdef CONFIG_SYS_I2C_MXC
  329. /* i2c_num can be from 0 - 3 */
  330. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  331. {
  332. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  333. switch (i2c_num) {
  334. case 0:
  335. clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
  336. CCM_CCGR4_I2C0_CTRL_MASK);
  337. case 2:
  338. clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
  339. CCM_CCGR10_I2C2_CTRL_MASK);
  340. break;
  341. default:
  342. return -EINVAL;
  343. }
  344. return 0;
  345. }
  346. #endif