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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
  4. *
  5. * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
  6. *
  7. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  8. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  9. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  10. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  11. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  12. * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  13. */
  14. #include <asm-offsets.h>
  15. #include <config.h>
  16. #include <asm/system.h>
  17. #include <linux/linkage.h>
  18. #include <asm/armv7.h>
  19. /*************************************************************************
  20. *
  21. * Startup Code (reset vector)
  22. *
  23. * Do important init only if we don't start from memory!
  24. * Setup memory and board specific bits prior to relocation.
  25. * Relocate armboot to ram. Setup stack.
  26. *
  27. *************************************************************************/
  28. .globl reset
  29. .globl save_boot_params_ret
  30. .type save_boot_params_ret,%function
  31. #ifdef CONFIG_ARMV7_LPAE
  32. .global switch_to_hypervisor_ret
  33. #endif
  34. reset:
  35. /* Allow the board to save important registers */
  36. b save_boot_params
  37. save_boot_params_ret:
  38. #ifdef CONFIG_ARMV7_LPAE
  39. /*
  40. * check for Hypervisor support
  41. */
  42. mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
  43. and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
  44. cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
  45. beq switch_to_hypervisor
  46. switch_to_hypervisor_ret:
  47. #endif
  48. /*
  49. * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
  50. * except if in HYP mode already
  51. */
  52. mrs r0, cpsr
  53. and r1, r0, #0x1f @ mask mode bits
  54. teq r1, #0x1a @ test for HYP mode
  55. bicne r0, r0, #0x1f @ clear all mode bits
  56. orrne r0, r0, #0x13 @ set SVC mode
  57. orr r0, r0, #0xc0 @ disable FIQ and IRQ
  58. msr cpsr,r0
  59. /*
  60. * Setup vector:
  61. * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  62. * Continue to use ROM code vector only in OMAP4 spl)
  63. */
  64. #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
  65. /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
  66. mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
  67. bic r0, #CR_V @ V = 0
  68. mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
  69. #ifdef CONFIG_HAS_VBAR
  70. /* Set vector address in CP15 VBAR register */
  71. ldr r0, =_start
  72. mcr p15, 0, r0, c12, c0, 0 @Set VBAR
  73. #endif
  74. #endif
  75. /* the mask ROM code should have PLL and others stable */
  76. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  77. #ifdef CONFIG_CPU_V7A
  78. bl cpu_init_cp15
  79. #endif
  80. #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  81. bl cpu_init_crit
  82. #endif
  83. #endif
  84. bl _main
  85. /*------------------------------------------------------------------------------*/
  86. ENTRY(c_runtime_cpu_setup)
  87. /*
  88. * If I-cache is enabled invalidate it
  89. */
  90. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  91. mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
  92. mcr p15, 0, r0, c7, c10, 4 @ DSB
  93. mcr p15, 0, r0, c7, c5, 4 @ ISB
  94. #endif
  95. bx lr
  96. ENDPROC(c_runtime_cpu_setup)
  97. /*************************************************************************
  98. *
  99. * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  100. * __attribute__((weak));
  101. *
  102. * Stack pointer is not yet initialized at this moment
  103. * Don't save anything to stack even if compiled with -O0
  104. *
  105. *************************************************************************/
  106. ENTRY(save_boot_params)
  107. b save_boot_params_ret @ back to my caller
  108. ENDPROC(save_boot_params)
  109. .weak save_boot_params
  110. #ifdef CONFIG_ARMV7_LPAE
  111. ENTRY(switch_to_hypervisor)
  112. b switch_to_hypervisor_ret
  113. ENDPROC(switch_to_hypervisor)
  114. .weak switch_to_hypervisor
  115. #endif
  116. /*************************************************************************
  117. *
  118. * cpu_init_cp15
  119. *
  120. * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
  121. * CONFIG_SYS_ICACHE_OFF is defined.
  122. *
  123. *************************************************************************/
  124. ENTRY(cpu_init_cp15)
  125. /*
  126. * Invalidate L1 I/D
  127. */
  128. mov r0, #0 @ set up for MCR
  129. mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
  130. mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
  131. mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
  132. mcr p15, 0, r0, c7, c10, 4 @ DSB
  133. mcr p15, 0, r0, c7, c5, 4 @ ISB
  134. /*
  135. * disable MMU stuff and caches
  136. */
  137. mrc p15, 0, r0, c1, c0, 0
  138. bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
  139. bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
  140. orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
  141. orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
  142. #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  143. bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
  144. #else
  145. orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
  146. #endif
  147. mcr p15, 0, r0, c1, c0, 0
  148. #ifdef CONFIG_ARM_ERRATA_716044
  149. mrc p15, 0, r0, c1, c0, 0 @ read system control register
  150. orr r0, r0, #1 << 11 @ set bit #11
  151. mcr p15, 0, r0, c1, c0, 0 @ write system control register
  152. #endif
  153. #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
  154. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  155. orr r0, r0, #1 << 4 @ set bit #4
  156. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  157. #endif
  158. #ifdef CONFIG_ARM_ERRATA_743622
  159. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  160. orr r0, r0, #1 << 6 @ set bit #6
  161. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  162. #endif
  163. #ifdef CONFIG_ARM_ERRATA_751472
  164. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  165. orr r0, r0, #1 << 11 @ set bit #11
  166. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  167. #endif
  168. #ifdef CONFIG_ARM_ERRATA_761320
  169. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  170. orr r0, r0, #1 << 21 @ set bit #21
  171. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  172. #endif
  173. #ifdef CONFIG_ARM_ERRATA_845369
  174. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  175. orr r0, r0, #1 << 22 @ set bit #22
  176. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  177. #endif
  178. mov r5, lr @ Store my Caller
  179. mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
  180. mov r3, r1, lsr #20 @ get variant field
  181. and r3, r3, #0xf @ r3 has CPU variant
  182. and r4, r1, #0xf @ r4 has CPU revision
  183. mov r2, r3, lsl #4 @ shift variant field for combined value
  184. orr r2, r4, r2 @ r2 has combined CPU variant + revision
  185. /* Early stack for ERRATA that needs into call C code */
  186. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
  187. ldr r0, =(CONFIG_SPL_STACK)
  188. #else
  189. ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
  190. #endif
  191. bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
  192. mov sp, r0
  193. #ifdef CONFIG_ARM_ERRATA_798870
  194. cmp r2, #0x30 @ Applies to lower than R3p0
  195. bge skip_errata_798870 @ skip if not affected rev
  196. cmp r2, #0x20 @ Applies to including and above R2p0
  197. blt skip_errata_798870 @ skip if not affected rev
  198. mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
  199. orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
  200. push {r1-r5} @ Save the cpu info registers
  201. bl v7_arch_cp15_set_l2aux_ctrl
  202. isb @ Recommended ISB after l2actlr update
  203. pop {r1-r5} @ Restore the cpu info - fall through
  204. skip_errata_798870:
  205. #endif
  206. #ifdef CONFIG_ARM_ERRATA_801819
  207. cmp r2, #0x24 @ Applies to lt including R2p4
  208. bgt skip_errata_801819 @ skip if not affected rev
  209. cmp r2, #0x20 @ Applies to including and above R2p0
  210. blt skip_errata_801819 @ skip if not affected rev
  211. mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
  212. and r0, r0, #1 << 3 @ check REVIDR[3]
  213. cmp r0, #1 << 3
  214. beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
  215. mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
  216. orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
  217. @ lines allocate in the L1 or L2 cache.
  218. orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
  219. @ lines allocate in the L1 cache.
  220. push {r1-r5} @ Save the cpu info registers
  221. bl v7_arch_cp15_set_acr
  222. pop {r1-r5} @ Restore the cpu info - fall through
  223. skip_errata_801819:
  224. #endif
  225. #ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
  226. mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
  227. orr r0, r0, #1 << 0 @ Enable invalidates of BTB
  228. push {r1-r5} @ Save the cpu info registers
  229. bl v7_arch_cp15_set_acr
  230. pop {r1-r5} @ Restore the cpu info - fall through
  231. #endif
  232. #ifdef CONFIG_ARM_ERRATA_454179
  233. mrc p15, 0, r0, c1, c0, 1 @ Read ACR
  234. cmp r2, #0x21 @ Only on < r2p1
  235. orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
  236. push {r1-r5} @ Save the cpu info registers
  237. bl v7_arch_cp15_set_acr
  238. pop {r1-r5} @ Restore the cpu info - fall through
  239. #endif
  240. #if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715)
  241. mrc p15, 0, r0, c1, c0, 1 @ Read ACR
  242. #ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715
  243. orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA
  244. #else
  245. cmp r2, #0x21 @ Only on < r2p1
  246. orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
  247. #endif
  248. push {r1-r5} @ Save the cpu info registers
  249. bl v7_arch_cp15_set_acr
  250. pop {r1-r5} @ Restore the cpu info - fall through
  251. #endif
  252. #ifdef CONFIG_ARM_ERRATA_621766
  253. mrc p15, 0, r0, c1, c0, 1 @ Read ACR
  254. cmp r2, #0x21 @ Only on < r2p1
  255. orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
  256. push {r1-r5} @ Save the cpu info registers
  257. bl v7_arch_cp15_set_acr
  258. pop {r1-r5} @ Restore the cpu info - fall through
  259. #endif
  260. #ifdef CONFIG_ARM_ERRATA_725233
  261. mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
  262. cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
  263. orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
  264. push {r1-r5} @ Save the cpu info registers
  265. bl v7_arch_cp15_set_l2aux_ctrl
  266. pop {r1-r5} @ Restore the cpu info - fall through
  267. #endif
  268. #ifdef CONFIG_ARM_ERRATA_852421
  269. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  270. orr r0, r0, #1 << 24 @ set bit #24
  271. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  272. #endif
  273. #ifdef CONFIG_ARM_ERRATA_852423
  274. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  275. orr r0, r0, #1 << 12 @ set bit #12
  276. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  277. #endif
  278. mov pc, r5 @ back to my caller
  279. ENDPROC(cpu_init_cp15)
  280. #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
  281. !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
  282. /*************************************************************************
  283. *
  284. * CPU_init_critical registers
  285. *
  286. * setup important registers
  287. * setup memory timing
  288. *
  289. *************************************************************************/
  290. ENTRY(cpu_init_crit)
  291. /*
  292. * Jump to board specific initialization...
  293. * The Mask ROM will have already initialized
  294. * basic memory. Go here to bump up clock rate and handle
  295. * wake up conditions.
  296. */
  297. b lowlevel_init @ go setup pll,mux,memory
  298. ENDPROC(cpu_init_crit)
  299. #endif