psci.S 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
  5. */
  6. #include <config.h>
  7. #include <linux/linkage.h>
  8. #include <asm/armv7.h>
  9. #include <asm/arch-armv7/generictimer.h>
  10. #include <asm/psci.h>
  11. #define RCPM_TWAITSR 0x04C
  12. #define SCFG_CORE0_SFT_RST 0x130
  13. #define SCFG_CORESRENCR 0x204
  14. #define DCFG_CCSR_RSTCR 0x0B0
  15. #define DCFG_CCSR_RSTCR_RESET_REQ 0x2
  16. #define DCFG_CCSR_BRR 0x0E4
  17. #define DCFG_CCSR_SCRATCHRW1 0x200
  18. #define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
  19. #define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
  20. #define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
  21. #define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
  22. #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
  23. #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
  24. #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
  25. #define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
  26. .pushsection ._secure.text, "ax"
  27. .arch_extension sec
  28. .align 5
  29. #define ONE_MS (COUNTER_FREQUENCY / 1000)
  30. #define RESET_WAIT (30 * ONE_MS)
  31. .globl psci_version
  32. psci_version:
  33. movw r0, #0
  34. movt r0, #1
  35. bx lr
  36. _ls102x_psci_supported_table:
  37. .word ARM_PSCI_0_2_FN_PSCI_VERSION
  38. .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
  39. .word ARM_PSCI_0_2_FN_CPU_SUSPEND
  40. .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
  41. .word ARM_PSCI_0_2_FN_CPU_OFF
  42. .word PSCI_FN_CPU_OFF_FEATURE_MASK
  43. .word ARM_PSCI_0_2_FN_CPU_ON
  44. .word PSCI_FN_CPU_ON_FEATURE_MASK
  45. .word ARM_PSCI_0_2_FN_AFFINITY_INFO
  46. .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
  47. .word ARM_PSCI_0_2_FN_SYSTEM_OFF
  48. .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
  49. .word ARM_PSCI_0_2_FN_SYSTEM_RESET
  50. .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
  51. .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
  52. .word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
  53. .word 0
  54. .word ARM_PSCI_RET_NI
  55. .globl psci_features
  56. psci_features:
  57. adr r2, _ls102x_psci_supported_table
  58. 1: ldr r3, [r2]
  59. cmp r3, #0
  60. beq out_psci_features
  61. cmp r1, r3
  62. addne r2, r2, #8
  63. bne 1b
  64. out_psci_features:
  65. ldr r0, [r2, #4]
  66. bx lr
  67. @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
  68. @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
  69. @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
  70. @ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
  71. LENTRY(psci_check_target_cpu_id)
  72. @ Get the real CPU number
  73. and r4, r1, #0xff
  74. mov r0, #ARM_PSCI_RET_INVAL
  75. @ Bit[31:24], bits must be zero.
  76. tst r1, #0xff000000
  77. bxne lr
  78. @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
  79. tst r1, #0xff0000
  80. bxne lr
  81. @ Affinity level 1 - Processors: should be in 0xf00 format.
  82. lsr r1, r1, #8
  83. teq r1, #0xf
  84. bxne lr
  85. @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
  86. cmp r4, #2
  87. bxge lr
  88. mov r0, #ARM_PSCI_RET_SUCCESS
  89. bx lr
  90. ENDPROC(psci_check_target_cpu_id)
  91. @ r1 = target CPU
  92. @ r2 = target PC
  93. .globl psci_cpu_on
  94. psci_cpu_on:
  95. push {r4, r5, r6, lr}
  96. @ Clear and Get the correct CPU number
  97. @ r1 = 0xf01
  98. bl psci_check_target_cpu_id
  99. cmp r0, #ARM_PSCI_RET_INVAL
  100. beq out_psci_cpu_on
  101. mov r0, r4
  102. mov r1, r2
  103. mov r2, r3
  104. bl psci_save
  105. mov r1, r4
  106. @ Get DCFG base address
  107. movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
  108. movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
  109. @ Detect target CPU state
  110. ldr r2, [r4, #DCFG_CCSR_BRR]
  111. rev r2, r2
  112. lsr r2, r2, r1
  113. ands r2, r2, #1
  114. beq holdoff_release
  115. @ Reset target CPU
  116. @ Get SCFG base address
  117. movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
  118. movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
  119. @ Enable CORE Soft Reset
  120. movw r5, #0
  121. movt r5, #(1 << 15)
  122. rev r5, r5
  123. str r5, [r0, #SCFG_CORESRENCR]
  124. @ Get CPUx offset register
  125. mov r6, #0x4
  126. mul r6, r6, r1
  127. add r2, r0, r6
  128. @ Do reset on target CPU
  129. movw r5, #0
  130. movt r5, #(1 << 15)
  131. rev r5, r5
  132. str r5, [r2, #SCFG_CORE0_SFT_RST]
  133. @ Wait target CPU up
  134. timer_wait r2, RESET_WAIT
  135. @ Disable CORE soft reset
  136. mov r5, #0
  137. str r5, [r0, #SCFG_CORESRENCR]
  138. holdoff_release:
  139. @ Release on target CPU
  140. ldr r2, [r4, #DCFG_CCSR_BRR]
  141. mov r6, #1
  142. lsl r6, r6, r1 @ 32 bytes per CPU
  143. rev r6, r6
  144. orr r2, r2, r6
  145. str r2, [r4, #DCFG_CCSR_BRR]
  146. @ Set secondary boot entry
  147. ldr r6, =psci_cpu_entry
  148. rev r6, r6
  149. str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
  150. isb
  151. dsb
  152. @ Return
  153. mov r0, #ARM_PSCI_RET_SUCCESS
  154. out_psci_cpu_on:
  155. pop {r4, r5, r6, lr}
  156. bx lr
  157. .globl psci_cpu_off
  158. psci_cpu_off:
  159. bl psci_cpu_off_common
  160. 1: wfi
  161. b 1b
  162. .globl psci_affinity_info
  163. psci_affinity_info:
  164. push {lr}
  165. mov r0, #ARM_PSCI_RET_INVAL
  166. @ Verify Affinity level
  167. cmp r2, #0
  168. bne out_affinity_info
  169. bl psci_check_target_cpu_id
  170. cmp r0, #ARM_PSCI_RET_INVAL
  171. beq out_affinity_info
  172. mov r1, r4
  173. @ Get RCPM base address
  174. movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
  175. movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
  176. mov r0, #PSCI_AFFINITY_LEVEL_ON
  177. @ Detect target CPU state
  178. ldr r2, [r4, #RCPM_TWAITSR]
  179. rev r2, r2
  180. lsr r2, r2, r1
  181. ands r2, r2, #1
  182. beq out_affinity_info
  183. mov r0, #PSCI_AFFINITY_LEVEL_OFF
  184. out_affinity_info:
  185. pop {pc}
  186. .globl psci_system_reset
  187. psci_system_reset:
  188. @ Get DCFG base address
  189. movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
  190. movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
  191. mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
  192. rev r2, r2
  193. str r2, [r1, #DCFG_CCSR_RSTCR]
  194. 1: wfi
  195. b 1b
  196. .globl psci_system_suspend
  197. psci_system_suspend:
  198. push {lr}
  199. bl ls1_system_suspend
  200. pop {pc}
  201. .popsection