fsl_ls1_serdes.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/arch/fsl_serdes.h>
  7. #include <asm/arch/immap_ls102xa.h>
  8. #include <linux/errno.h>
  9. #include <asm/io.h>
  10. #include "fsl_ls1_serdes.h"
  11. #ifdef CONFIG_SYS_FSL_SRDS_1
  12. static u64 serdes1_prtcl_map;
  13. #endif
  14. #ifdef CONFIG_SYS_FSL_SRDS_2
  15. static u64 serdes2_prtcl_map;
  16. #endif
  17. int is_serdes_configured(enum srds_prtcl device)
  18. {
  19. u64 ret = 0;
  20. #ifdef CONFIG_SYS_FSL_SRDS_1
  21. if (!(serdes1_prtcl_map & (1ULL << NONE)))
  22. fsl_serdes_init();
  23. ret |= (1ULL << device) & serdes1_prtcl_map;
  24. #endif
  25. #ifdef CONFIG_SYS_FSL_SRDS_2
  26. if (!(serdes2_prtcl_map & (1ULL << NONE)))
  27. fsl_serdes_init();
  28. ret |= (1ULL << device) & serdes2_prtcl_map;
  29. #endif
  30. return !!ret;
  31. }
  32. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  33. {
  34. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  35. u32 cfg = in_be32(&gur->rcwsr[4]);
  36. int i;
  37. switch (sd) {
  38. #ifdef CONFIG_SYS_FSL_SRDS_1
  39. case FSL_SRDS_1:
  40. cfg &= RCWSR4_SRDS1_PRTCL_MASK;
  41. cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  42. break;
  43. #endif
  44. #ifdef CONFIG_SYS_FSL_SRDS_2
  45. case FSL_SRDS_2:
  46. cfg &= RCWSR4_SRDS2_PRTCL_MASK;
  47. cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
  48. break;
  49. #endif
  50. default:
  51. printf("invalid SerDes%d\n", sd);
  52. break;
  53. }
  54. /* Is serdes enabled at all? */
  55. if (unlikely(cfg == 0))
  56. return -ENODEV;
  57. for (i = 0; i < SRDS_MAX_LANES; i++) {
  58. if (serdes_get_prtcl(sd, cfg, i) == device)
  59. return i;
  60. }
  61. return -ENODEV;
  62. }
  63. u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
  64. {
  65. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  66. u64 serdes_prtcl_map = 0;
  67. u32 cfg;
  68. int lane;
  69. cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
  70. cfg >>= sd_prctl_shift;
  71. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  72. if (!is_serdes_prtcl_valid(sd, cfg))
  73. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  74. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  75. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  76. serdes_prtcl_map |= (1ULL << lane_prtcl);
  77. }
  78. /* Set the first bit to indicate serdes has been initialized */
  79. serdes_prtcl_map |= (1ULL << NONE);
  80. return serdes_prtcl_map;
  81. }
  82. void fsl_serdes_init(void)
  83. {
  84. #ifdef CONFIG_SYS_FSL_SRDS_1
  85. if (!(serdes1_prtcl_map & (1ULL << NONE)))
  86. serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
  87. CONFIG_SYS_FSL_SERDES_ADDR,
  88. RCWSR4_SRDS1_PRTCL_MASK,
  89. RCWSR4_SRDS1_PRTCL_SHIFT);
  90. #endif
  91. #ifdef CONFIG_SYS_FSL_SRDS_2
  92. if (!(serdes2_prtcl_map & (1ULL << NONE)))
  93. serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
  94. CONFIG_SYS_FSL_SERDES_ADDR +
  95. FSL_SRDS_2 * 0x1000,
  96. RCWSR4_SRDS2_PRTCL_MASK,
  97. RCWSR4_SRDS2_PRTCL_SHIFT);
  98. #endif
  99. }
  100. const char *serdes_clock_to_string(u32 clock)
  101. {
  102. switch (clock) {
  103. case SRDS_PLLCR0_RFCK_SEL_100:
  104. return "100";
  105. case SRDS_PLLCR0_RFCK_SEL_125:
  106. return "125";
  107. default:
  108. return "100";
  109. }
  110. }